multiple write in MessageQ IPC in DSP C6670

Nedal Elhelw1

I use IPC in DSP C6670, Core0 create massageQ and read it and core1, core2, core3 write messages to core0 in this messageQ. The problem is Core0 sometimes receives same message twice (core 0 receives more packets than the sender), I assume because collation from multiple write at the same time since if I have only one writes there is no problem.

I used gateMP, by including header file and defined in cfg. I understand that gateMP already in messageQ and not need to start. My IPC section in cfg is

var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');

* Get the list of names that the build device supports.

* I.e. ["CORE0", "CORE1", "CORE2" ... ]

var nameList = MultiProc.getDeviceProcNames();

* Since this is a single-image example, we don't (at build-time) which

* processor we're building for. We therefore supply 'null'

* as the local procName and use MultiProc_setLocalId to set the procId

* at runtime.

MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2"/*, "CORE3"*/]);

var SysStd = xdc.useModule('xdc.runtime.SysStd');

System.SupportProxy = SysStd;

/* Modules explicitly used in the application */

var Settings = xdc.module('ti.sdo.ipc.family.Settings');

var MessageQ = xdc.module('ti.sdo.ipc.MessageQ');

var Notify = xdc.module('ti.sdo.ipc.Notify');

var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');

var listMp = xdc.useModule('ti.sdo.ipc.ListMP');

var GateMP = xdc.useModule('ti.sdo.ipc.GateMP');

Notify.SetupProxy = xdc.module(Settings.getNotifySetupDelegate());

MessageQ.SetupTransportProxy= xdc.module(Settings.getMessageQSetupDelegate());

/* Use shared memory IPC */

Notify.SetupProxy = xdc.module('ti.sdo.ipc.family.c647x.NotifyCircSetup');

MessageQ.SetupTransportProxy = xdc.module('ti.sdo.ipc.transports.TransportShmNotifySetup');

/* Synchronize all processors (this will be done in Ipc_start) */

Ipc.procSync = Ipc.ProcSync_ALL;

/* Shared Memory base address and length */

var SHAREDMEM = 0x98000000;

var SHAREDMEMSIZE = 0x00700000;

* Need to define the shared region. The IPC modules use this

* to make portable pointers. All processors need to add this

* call with their base address of the shared memory region.

* If the processor cannot access the memory, do not add it.

var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');

SharedRegion.translate = false;

SharedRegion.setEntryMeta(0,

{ base: SHAREDMEM,

len: SHAREDMEMSIZE,

ownerProcId: 0,

isValid: true,

cacheEnable: true,

cacheLineSize: 128, /* Aligns allocated messages to a cache line */

name: "MSMCSRAM_IPC",

createHeap: true,

});

I used IPC 1.25.3.15 and sys/Bios 6.35.1.29.

Can anybody help me to solve this problem?

over 11 years ago

0 Pubesh over 11 years ago

TI__Mastermind 20790 points

Hi,

Is your own configuration for IPC or take the reference cfg?
IPC based demo avilable at MCSDK package. See the below path,
<MCSDK INSTALL DIR>\demos\image_processing\ipc
This will give you how to use the IPC between the Master(core 0) and Slave(core1, core2, core3).
Find the IPC flow and what are the configuration needs for IPC using shared memory at this wiki,
http://processors.wiki.ti.com/index.php/BIOS_MCSDK_2.0_User_Guide#Shared_Memory_IPC_Transport
http://processors.wiki.ti.com/index.php/BIOS_MCSDK_2.0_User_Guide#Multi-core_Programming_Models
If you like to go for multicore navigator, see the test code as per below path.
The QMSS IPC Transport benchmark example is available in
$(TI_PDK_C667x_INSTALL_DIR)\packages\ti\transport\ipc\examples\qmssIpcBenchmark

I do not know how you are running the application on cores.
You can try to make a group for slave and master.
Keep master core0, group the rest of slave cores and run.

Please check the configuration file(.cfg) for master as per below,
/* Load and configure the IPC packages */
var MessageQ     = xdc.useModule('ti.sdo.ipc.MessageQ');
var Ipc          = xdc.useModule('ti.sdo.ipc.Ipc');
var HeapBufMP    = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
var MultiProc    = xdc.useModule('ti.sdo.utils.MultiProc');

MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2", "CORE3"]);

/* Synchronize all processors (this will be done in Ipc_start) */
Ipc.procSync = Ipc.ProcSync_ALL;

/* Shared Memory base address and length */
var SHAREDMEM = 0x0C180000;
var SHAREDMEMSIZE = 0x00080000;

SharedRegion.setEntryMeta(0,
    { base: SHAREDMEM,
      len: SHAREDMEMSIZE,
      ownerProcId: 0,
      isValid: true,
      name: "MSMCSRAM_IPC",
    });

Please check the configuration file(.cfg) for slave as per below,

/* Load and configure the IPC packages */
var MessageQ     = xdc.useModule('ti.sdo.ipc.MessageQ');
var Ipc          = xdc.useModule('ti.sdo.ipc.Ipc');
var HeapBufMP    = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
var MultiProc    = xdc.useModule('ti.sdo.utils.MultiProc');

MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2", "CORE3"]);

/* Synchronize all processors (this will be done in Ipc_start) */
Ipc.procSync = Ipc.ProcSync_ALL;

/* Shared Memory base address and length */
var SHAREDMEM = 0x0C180000;
var SHAREDMEMSIZE = 0x00080000;

SharedRegion.setEntryMeta(0,
    { base: SHAREDMEM,
      len: SHAREDMEMSIZE,
      ownerProcId: 0,
      isValid: true,
      name: "MSMCSRAM_IPC",
    });
Memory.defaultHeapSize = 0x10000;
Program.heap = 0x10000;

0 Nedal Elhelw1 over 11 years ago in reply to Pubesh

Prodigy 90 points

I solve the issue by rewriting cfg. I remove

Notify.SetupProxy = xdc.module('ti.sdo.ipc.family.c647x.NotifyCircSetup');

It sounds that cause the problem. I got that line from shmIpcBenchmark_c6670 example which I assume it is safe.

I don't use notify in my setup, but it is better to understand the cause of the problem.

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multiple write in MessageQ IPC in DSP C6670