C6678 SRIO CLOCKS (IP_CLK and SRV_CLK)

Hi Gabriele,

Have you taken a look at the following post?

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/282116.aspx

Thanks,

Clinton

so SRV_CLK =  IP_CLK  / PRESCALAR_SRV_CLK ?

and IP_CLK = TXBCLK = 1/20th of my data rate ? (5Gbaud -> TXBCLK = 250Mhz)

It's Correct?

Ok, but but in the discussion that you linked is said that it is correct to assume that the SRV_CLK is the Prescaled IP_CLK

"Does the SRV_CLK mean the Prescaled IP_CLK? If so, the equation of Silence timer interval as follows:

Silence timer interval = Prescaled IP_CLK period x 410 x SILENCE_TIMER, where the Prescaled IP_CLK period = (IP_CLK period * RIO_IP_PRESCAL value)."

"Yes you are correct, the silence timer would be treated the same way as the Discovery timer, just a different multiplier.  Your equation is correct."

I'm a little confused...

Hi Gabriele,

The srv_clk is the internal bus frequency, which is CPU/3.

Refer section 3.17.74 in SRIO user guide (sprugw1b) for IP_CLK prescaler.

Thanks,

ok, and even the DMA Clock Period is the same as the VBUS Clock and is CPU/3, right?

Yes the DMA Clock Period is same as the VBUS Clock (CPU/3).

Thanks,