Questions regarding global variable allocation in memory

Renaissance

Based on pre-defined .cmd file as following

/* Memory Map 1 - the default */
MEMORY
{
     vecs:    o = 00000000h   l = 00000200h
        boot:    o = 00000200h   l = 00000200h
    L1D:     o = 00f00000h   l = 00008000h
        L1P:     o = 00e00000h   l = 00008000h
        L2:      o = 00800000h   l = 00200000h
  DDR2: o = 0e0000000h l = 010000000h
}

SECTIONS
{
    .csl_vect   >       vecs
.text  >       DDR2
    .stack      >       L2
    .bss        >       L2
    .cinit      >       L2
    .cio        >       L2
    .const      >       L2
    .switch     >       L2
    .sysmem     >       DDR2
    .far        >       L2
    .testMem    >       L2
    ISRAM       >       L2
    .image     >       DDR2
}

Then, in my program, I made the following allocation for several variables

#pragma DATA_SECTION(ext_buffer, ".image:tsd_input");
#pragma DATA_SECTION(center_tp, ".image:ext_sect0");
#pragma DATA_SECTION(P10_reg_tp, ".image:ext_sect1");
#pragma DATA_SECTION(N10_reg_tp, ".image:ext_sect2");
#pragma DATA_SECTION(sc_LUT, ".image:ext_sect_3");
#pragma DATA_SECTION(post_sc_image, ".image:ext_sect_4");

short ext_buffer[NUMBER_OF_SCANLINE*NUM_CHANNEL*NUM_AXIAL_SAMPLES]; 0xE01A 8978
unsigned short center_tp[NO_INPUT_SAMPLE*NO_OUTPUT_VECTOR];                      0xE000 0000
unsigned short P10_reg_tp[NO_OUTPUT_SAMPLE*NO_OUTPUT_VECTOR];             0xE006 2000
unsigned short N10_reg_tp[NO_OUTPUT_SAMPLE*NO_OUTPUT_VECTOR];             0xE00C 4000
unsigned char post_sc_image[NO_POSTSC_WIDTH*NO_POSTSC_HEIGHT];             0xE012 6000
unsigned char sc_LUT[NO_BYTES_PER_LUT_ENTRY*NO_OUTPUT_PIXELS];          0xE017 1000

In the symbol browser window, I can see the above 6 arrays have been allocated in the DDR address as I show above in red font. I am wondering, how these arrays have been allocated based on the above order? Why is ext_buffer not in the beginning of the DDR memory, but the center_tp? Can I have more control of this?

Thank you very much.

over 16 years ago

0 Mariana over 16 years ago

TI__Mastermind 24340 points

The linker order is usually by size, but that is not guaranteed.

Also, there is no guarantee that the linker will allocate output sections in the order they are listed in the linker command file.

You can order the sections/vector using GROUP directive. This FAQ should give you some background on how the current linker handles input and output sections, and shows how to use the GROUP directive to place output sections in memory in a specific order:

http://www-k.ext.ti.com/SRVS/CGI-BIN/WEBCGI.EXE/,/?St=9,E=0000000000013743017,K=6896,Sxi=0,Case=obj(52803)

Please also see an example at this forum post.

0 TimHarron over 16 years ago in reply to Mariana

TI__Mastermind 18130 points

You can try the --default_order linker switch to disable size-based allocation, but I am not sure that this is going to give you anymore control over where the linker places code/data segments. The only way I know of to guarantee the order in which the linker places a section is to create smaller memory segments and place each section to its own segment, but as you can imagine this is going to be tedious and time-consuming.

0 Renaissance over 16 years ago in reply to Mariana

Intellectual 925 points

Thank you, Mariana. I will read.

0 Renaissance over 16 years ago in reply to TimHarron

Intellectual 925 points

Thank you Tim.

I think this is a valid solution since I only have to make one array at specic location. Here is what I did.

SECTIONS
{
    .csl_vect   >       vecs
.text  >       DDR2
    .stack      >       L2
    .bss        >       L2
    .cinit      >       L2
    .cio        >       L2
    .const      >       L2
    .data       >       L2
    .switch     >       L2
    .sysmem     >       DDR2
    .far        >       L2
    .testMem    >       L2
    ISRAM       >       L2
.chip_image >       L2
.pp_buf     >       L1D
    .image     >       DDR2
.rfimage    >  RF_DDR2
}

Then in my code, I did the following so that the ext_buffer array is in the memory at the location 0e000 0000.

#pragma DATA_SECTION(ext_buffer, ".rfimage:tsd_input");

short ext_buffer[NUMBER_OF_SCANLINE*NUM_CHANNEL*NUM_AXIAL_SAMPLES]; 0xE000 0000
unsigned short center_tp[NO_INPUT_SAMPLE*NO_OUTPUT_VECTOR];                      0xE002 0000
unsigned short P10_reg_tp[NO_OUTPUT_SAMPLE*NO_OUTPUT_VECTOR];             0xE008 2000
unsigned short N10_reg_tp[NO_OUTPUT_SAMPLE*NO_OUTPUT_VECTOR];             0xE00E 4000
unsigned char post_sc_image[NO_POSTSC_WIDTH*NO_POSTSC_HEIGHT];             0xE014 6000
unsigned char sc_LUT[NO_BYTES_PER_LUT_ENTRY*NO_OUTPUT_PIXELS];          0xE019 1000

Now, you can see the order can be changed and the ext_buffer is located at a new place.

Thank you very much,

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Questions regarding global variable allocation in memory