Should I maintain cache coherency between L2 SRAM and L1D cache in 6678?

steve zhang

Expert 1690 points

Hi,all:

Does cache coherency between L2SRAM and L1D cache on 6678 need to be maintained by myself

or automatically by Hardware?

Can I set cache size of L1D to 0?

over 11 years ago

0 HRi over 11 years ago

Guru 10750 points

Hi Steve,

1- for each DSP the HW maintain the coherency between L1 cache and L2-SRAM,

2- Yes You can configure L1D to be all RAM ( zero cache)

Thanks,

0 one and zero over 11 years ago

TI__Mastermind 18136 points

Hi,

1. Cache coherence between L2 and L1D is maintained by HW. The C66x L1D cache remains coherent with respect to DMA activity in L2 RAM. For details please see:

http://www.ti.com/lit/pdf/sprugy8

2. Yes this is possible in L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac.Configurable L1D cache size: 0K, 4K, 8K, 16K, 32K. For details please see:

http://www.ti.com/lit/pdf/sprugw0

Kind regards,

one and zero

Processors

Processors forum

Should I maintain cache coherency between L2 SRAM and L1D cache in 6678?