Problem with PCIe Read Memory Request

Hello all.

I'm having problem with PCIe Read Memory Request.

My configuration setting:

    C6678 is Root Complex and FPGA (Virtex-6) is End Point;
    Reference clock frequency 100MHz;
    Number of lanes x1;
    BAR[1:0] - 64 bit, 2 Kbytes;
    BAR[2] - 32 bit, prefetchable, 2 Kbytes;
    Outbound translation is enable;

I'm just trying to Write/Read 1 dword to/from FPGA by C6678.

1. I'm writing data (0xFACEFACE) to Addr:0x60000004 - OK (I saw this transaction on FPGA endpoint interface);

2.Then, I am reading data from Addr:0x6000004 and the result is wrong.

But I saw on FPGA PIPE_TX interface completion header with data I expect:

FB 00 7A

4A 00 80 01 (Fmt | Type = 4A - Completion with data, Lenght = 1 dword)

00 00 00 04 (Completion ID = 00, Byte count = 4)

00 00 1A 04 (Request ID = 00, Tag = 1A, Lower Address = 04)

FA CE FA CE (data)

What kind of thing will cause problem ?

How can I verify, that C6678 receive this completion header and where can I find return data for my request?

Tnank You,

Andrey B.