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Set EMU0/EMU1 as GPIO at u-boot

Eric Lee4
Expert 1285 points

I am working on an AM335X custom board. The board has 12 GPIOs. I have no problems in controlling the GPIOs in u-boot except the emu0(gpio3_7) and emu1(gpio3_8). It seems that they always stay at high no matter what value I set. 

How to set the emu0/emu1 as a GPIO at u-boot? Is there something needed to be specially cared?

-Eric 

  • 0
    TI__Mastermind 25235 points

    Hi Eric,

    Are you sure there are no external pull-up resistors on these pins? Please share your U-Boot pinmux configuration.

    Best regards,
    Miroslav

  • 0 in reply to Miroslav Kiradzhiyski XID
    Expert 1285 points

    Miroslav,

    The emu0 is floating and no external pull-ups. I tested in the uboot command mode first by "gpio set 103" and "gpio clear 103" command and then measured the voltage rails. All other 11 GPIOs got correct results except the gpio3_7.

    I found there some notes in regarding to this in your Errata. 

    "If the EMU[1:0] terminals are configured to operate as GPIO, the product should be
    designed such these terminals can be pulled to a valid high-logic level within 190 ns
    after the falling edge of WARMRSTn."

    Is this related? Could you explain me more details?

    -Eric

  • 0 in reply to Eric Lee4
    TI__Guru 62875 points

    The state of terminals EMU0 and EMU1 are read on the rising edge of PWRONRSTn.  These inputs must be high when PWRONRSTn is released for the processor to enter normal code execution mode.  Advisory 1.0.36 describes the requirements for using EMU0 and EMU1 as GPIO to insure these inputs are high when PWRONRSTn is released.

    The potential issue described by Advisory 1.0.36 only effects the device operation when PRWONRSTn is released.  So if you system is booting and executing code, this Advisory is unrelated to toggling the GPIO outputs.

    I know at least one customer has been successful at using the EMU0 and EMU1 terminals as GPIO, because they found a large capacitive load on these terminals would not allow the signals to be pulled high fast enough if they were configured as GPIO outputs and driven low when PWRONRSTn was applied again.

    Regards,
    Paul

     

  • 0 in reply to Miroslav Kiradzhiyski XID
    Expert 1285 points

    We found that we did not solder a 0 ohm resister and the line is default disconnected. After soldering it, it is fine now.