Dear Support team,
I am trying to establish the connection between TCI6636K2H and TMS320C6678 over Hyperlink. I am using TI provided example for
hyperlink hyplnk_K2HC66BiosExampleProject(TMS320C6678) and hyplnk_exampleProject(for TMS320C6678) on custom board.
I also tested the loopback and as per previous TI support posts i can successfully able to test look back and its working.
As per the posts:
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/286514.aspx
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/292300/1020227.aspx
I have been using define hyplnk_EXAMPLE_SERRATE_06p250, 4 Lanes,
and #define hyplnk_EXAMPLE_REFCLK_312p50 for both shannon and Hawking Dsps for loopback .(Both DSPs are in NO BOOT MODE)
when i am trying to establish connection between TCI6636K2H and TMS320C6678 over Hyperlink both the DSPs crash. The console printf is shown below:
Looking at the console it seems that connection is established and serdes are trained. However application tried to
access the memory addresses responsible for the registers of the remote device, The application crashes.
Can you please let me know what wrong happening here?. Can you please also provide the steps needed for the connection between C6678 and TCI6636K2H .
2. Does the Link status register contents look correct ?
Shannon (TMS320C6678)--> pdk_C6678_1_1_2_6
Hawking (TCI6636K2H)--> pdk_keystone2_3_00_03_15 , mcsdk_bios_3_00_03_15
DSP0_0 is Hawking and DSP1_0 is shannon.
/******CONSOLE OUTPUT**********/
[DSP1_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:04:15
About to do system setup (PLL, PSC, and DDR)
Constructed SERDES configs: PLL=0x00000228; RX=0x0046c485; TX=0x000cc305
system setup worked
About to set up HyperLink Peripheral
============== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e901900
Status register contents:
Raw = 0x00002004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000001
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
[DSP0_0] Version #: 0x02000009; string HYPLNK LLD Revision: 02.00.00.09:Nov 24 2013:17:32:20
About to do system setup (PLL, PSC, and DDR)
Power domain is already enabled. You probably re-ran without device reset (which is OK)
Constructed SERDES configs: PLL=0x00000228; RX=0x0046c485; TX=0x000cc305
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 0
========================================== begin registers before initialization ===========
Revision register contents:
Raw = 0x4e902101
Status register contents:
Raw = 0x00003004
Link status register contents:
Raw = 0x00000000
Control register contents:
Raw = 0x00000001
Control register contents:
Raw = 0x00000000
============== end registers before initialization ===========
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
Link status register contents:
Raw = 0xccf00cff
Control register contents:
Raw = 0x00006200
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
[DSP1_0] Waiting for other side to come up ( 0)
SERDES_STS (32 bits) contents: 0x00102001; lock = 1
============== begin registers after initialization ===========
Status register contents:
Raw = 0x04400005
Link status register contents:
Raw = 0xccf00cf0
Control register contents:
Raw = 0x00006200
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
[DSP0_0] Precursors 0
Postcursors: 19
Link seems stable
About to try to read remote registers
[DSP1_0] Precursors 0 Analysis: 0,0,0,0,0,0,0,0
Postcursors: 19 Analysis: 0,0,0,0,0,0,0,0
Link seems stable
About to try to read remote registers
