SPI TXINTFLG set as soon as ENABLE is set

Hi,

Can you please check the "SPINT0.TXINTENA" bit and DMAREQEN  when you are enabling the SPIEN,

Please ensure that you are following SPI initialization sequence from chapter 30.2.19 in OMAPL138 TRM,

I should have given a little more information about my application.

I am using the EDMA to respond to the TXINTFLG conditions, generally speaking. I am not making use of the SPI TX Interrupt as such, so I did not set TXINTENA. I am setting DMAREQEN. As far as I can tell, I am following the sequence in 30.29.19 of SPRUH77A (OMAPL138 TRM).

During powerup, I am initializing the SPI, and then initializing the EDMA. As soon as I enable the EDMA to respond to the SPI TX indication as a trigger, the EDMA writes a word of data to SPIDAT0, thus starting an SPI transmit/receive sequence. I am assuming that the fact that this trigger occurs immediately is related to the fact that TXINTFLG is already set when the EDMA is enabled.

My problem is that I do not want to write a word of data to the SPI as soon as the EDMA is initialized. At a later time (post-initialization), I want to kick off my SPI transmit by writing a word by hand (not via EDMA) to SPIDAT0, and then the EDMA will deliver the rest of the message to SPI DAT0.

That's why I am asking about TXINTFLG. If TXINTFLG being set when the EDMA is initialized is resulting in an immediate trigger to the EDMA, it seems to me that I can produce the behavior I want by making sure that TXINTFLG is NOT set at initialization, and I'm trying to figure out how to make that happen.

If there is no way to clear TXINTFLG without causing an SPI transmit, then I think I can work around the issue, but I'm trying to find out for sure whether TXINTFLG is automatically set when the ENABLE bit is set in SPIGCR1.

Hi,

That's why I am asking about TXINTFLG. If TXINTFLG being set when the EDMA is initialized is resulting in an immediate trigger to the EDMA, it seems to me that I can produce the behavior I want by making sure that TXINTFLG is NOT set at initialization, and I'm trying to figure out how to make that happen.

TXINTFLG is Transmitter empty interrupt flag and will raise the interrupt when it is TXBUF is empty.

This flag ll get set as soon as SPI initialized because TXBUF not having any data (empty) to process such as copying data to shift reg.

My suggestion is that first do initialize the EDMA then SPI.

http://processors.wiki.ti.com/index.php/StarterWare_SPI

http://processors.wiki.ti.com/index.php/StarterWare_01.10.01.01_User_Guide#SPI

Please refer the SPI EDMA starterware code to understand the concepts of SPI EDMA and try to implement your use case in TI starterware and change it as per your requirement,

Please refer the SPIINT0 & SPIFLG register in chapter of SPI in TRM. (30.3.3 & 30.3.5)

Thanks for your fast response. I will investigate whether changing the relative position of the initialization of the SPI and the EDMA is an option. I am working on existing code and my options are sometimes limited because of that.

Let me ask you this, though. If I initialize EDMA and then initialize SPI, and TXINTFLG is set as soon as the SPI is ENABLEd, will a trigger to the EDMA channel that handles SPI transmit occur as soon as I write to the ENABLE bit for the SPI?

I ask because this is NOT actually the ideal behavior in my particular case. What I am trying to do is not have any SPI activity at initialization. I want to start the SPI transmite/receive at some point after initialization has completed and other events in my system have occurred, and I would start the process by writing to the SPI transmit data register by hand.

It has occured to me that one way I could produce this result would be to initialize the EDMA to do nothing with the first trigger from the SPI TX channel, and then have the EDMA channel transition to different handling of triggers after this initial trigger occurs. Does this sound like a viable path?