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DM- 8148 -EMAC- ping not working

Dear Sir/Madam,

We are using the TMS320DM814x  processor in our project.

We have used the linux kernel with PSP patch: linux-2.6.37-psp04.04.00.01

Further,we have compiled the kernel with following options

1."[*]Device Drivers"->"Network device support"->"PHY Device support and infrastructure"- - - >"Drivers for   Marvell PHYs" ( Marvell - We used the custom PHY driver).

2.[*] Networking support ---> Device Drivers --->

    [*]Network device support --->[*] Ethernet driver support --->

-*-     TI DaVinci MDIO Support  
-*- TI DaVinci CPDMA Support
-*- TI CPSW Switch Phy sel Support
<*> TI CPSW Switch Support

For the above configuration of kernel and booted with that image,After assigned the Ip address for the eth0 and try to ping.
The ping not working.When we seen the dmesg in the kernel log it shows the following log



Starting Bootlog daemon: bootlogd.
Configuring network interfaces... PHY 0:00 not found

CPSW phy found : id is : 0x1410dd1
udhcpc (v1.19.4) started
Sending discover...
PHY: 0:01 - Link is Up - 100/Full
Sending discover...
Sending discover...
No lease, failing
done.

Another observation is,when we tried to connect the board with PC both are locally connected by point to point.
When we tried the PING between these nodes We couldnt receive any packet capture observed in wireshark.


Could you help us to resolve this issue.

thanks
senthil nathan..






 

 

                                           

  • Hello,

    You are using DM814x based custom board with PHY different from the DM814x EVM PHY, is that the case?

    Make sure you go through all the steps described in the below wiki page:

    http://processors.wiki.ti.com/index.php/TI81xx_PSP_Porting_Guide#Ethernet_Driver_-_Adding_Custom_Ethernet_Phy

    Rajeshkumar R said:
    For the above configuration of kernel and booted with that image,After assigned the Ip address for the eth0 and try to ping.

    Can you try to test the ethernet connection between the DM814x board and PC at the u-boot stage, with ping/dhcp commands.

    Best regards,
    Pavel

  • Dear Pavel,

    http://processors.wiki.ti.com/index.php/TI81xx_PSP_Porting_Guide#Ethernet_Driver_-_Adding_Custom_Ethernet_Phy

    As per this guide it shows changes and configurations for "CPSW RMII Phy" and  CPSW MII Phy. 


    But we have need configuration and changes need for RGMII mode, could  you help us  regarding this.

     

    thanks

    senthil nathan.D.

  • Senthil,

    Rajeshkumar R said:
    But we have need configuration and changes need for RGMII mode

    You should verify the appropriate pin muxing for RGMII mode, see the DM814x datasheet and TRM for more info.

    Also you can find info regarding the RGMII mode in the below E2E threads:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/169742.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/321704.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/169257.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/252657.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/157535.aspx

    You can also check the DM8148 EVM. The EVM has two RGMII Ethernet port (RGMII0, RGMII1) using a two external PHY AR8031 which is interfaced to the processor via the RGMII interface.

    Best Regards,
    Pavel

  • Dear Pavel,
    I encounter the same problem and find it is the code "ti814x_sata_pllcfg();" in arch/arm/mach-omap2/devices.c,Line 2918 which causes the problem above under version 'ti-ezsdk_dm814x-evm_5_05_02_00'.
    Remove it and the problem gone.
    It is ok under version 'ti-ezsdk_dm814x-evm_5_04_00_11' since no such code in the corresponding file.
    But I wonder why it affects the NIC since it initializes the pll configuration of sata module.Is there any patches or new version of SDK.
    Hope your reply.
    Best Regards,
    Chen
  • Hi Chen,

    user4896477 said:
    But I wonder why it affects the NIC since it initializes the pll configuration of sata module

    SATA SerDes PLL provides the reference clock to the EMAC (Ethernet) module. For more details see the below pointers:

     DM814x TRM, sections 2.3.6 SERDES and Ethernet Clock Structure, 9.1.5 Clocking

    ti814x_sata_pllcfg() come in EZSDK 5.05 by the below patch:

    user4896477 said:
    Is there any patches or new version of SDK.

    There is no newer version of the EZSDK, 5.05.02.00 is the latest. The latest patches are available in the below location:

    Regards,
    Pavel