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Hyperlink Address Configuration

Senthil Kumar
Intellectual 505 points

Hi,

Could anybody clarify the following points on Hyperlink,

1. For data transfer b/w dsp1 and dsp2 what are the registers to be configured at DSP1 and DSP2

2. To exchange the data, dsp1 may read/write from 0x40000000 to 0x4FFFFFFF, how the dsp1 knows dsp2 memory region mapped to dsp1 hyperlink memory range(0x40000000 to 0x4FFFFFFF).

3. Usage for configuring " local tx and rx regs" and also "remote tx and rx regs"

Regards,

Senthil

  • 0
    TI__Mastermind 28085 points

    Hi Senthil,

    Refer TI MCSDK Hyperlink example project (\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\hyplnk_exampleProject) code. 

    Address Translation:

    - DSP1 (Tx) can view max. 256MB of DSP2 (Rx) memory**.
    - Tx side: HyperLink memory space is 0x4000_0000 to 0x4FFF_FFFF
    - Rx side: HyperLink memory space is device dependent, but typically somewhere in the 0x0000_0000 to 0xFFFF_FFFF address range (For example: DDR 0x8000_0000 to 0x8FFF_FFFF)
    - Requires mechanism to convert local (Tx) address to remote (Rx) address
    - The local side (Tx side) manipulates the address, the remote side (Rx) does address translation

    For more information about Hyperlink register configuration and memory map, refer HyperLink User Guide

    http://www.ti.com/lit/sprugw8

    Thanks,