Hello all.
I'm having problem with PCIe Inbound address translation.
My configuration setting:
- C6678 is Root Complex and FPGA (Virtex-6) is End Point;
- Reference clock frequency 100MHz;
- Number of lanes x1;
- Endpoint BAR[1:0] - 64 bit, 2 Kbytes;
- Endpoint BAR[2] - 32 bit, prefetchable, 2 Kbytes;
- Root BAR0 - 70000000h;
- Outbound translation is enable and work.
Root Inbound configuration:
- IB_BAR0 (300h) - 1;
- IB_START0_LO (304h) - 70000000h;
- IB_START0_Hi (308h) - 0h;
- IB_OFFSET0 (30Ch) - (uint32_t)pcieConvert_CoreLocal2GlobalAddr((uint32_t)dstBuf.buf) (local buffer - 00855C00 convert to global - 11855C00h);
I'm just trying to Write 1 dword (0000BEAF ) from FPGA to C6678 destination address 70000004h, but the result is wrong.
I saw on FPGA PIPE_TX interface this Memory Request:
- FB 00 9A
- 40 00 00 01 (Fmt | Type = 40 - Memory Request, Lenght = 1 dword)
- 01 00 00 0F (ReqID = 0100, LBE = 0, FBE = F)
- 70 00 00 04 (Address = 70000004h)
- AF BE 00 00 (Data = 0000BEAF)
What am I doing wrong ?
Tnank You,
Andrey B.
