Other Parts Discussed in Thread: OMAPL138
Hi!
I use a L138 LCDK CCS 5.5, SYS/BIOS 6.35.04.50 and pdk_OMAPL138_1_01_00_02.
I want to establish an UART communication with my PC via the FTDI 232 (UART2 @ L138).
I started my code by adapting the SYS/BIOS clock-demo.
I already receive characters at the pc side, but something is still messed up (e.g. the 2 msb are always 1, some bits seem to be flipped ...)
Furthermore (with the scope probing R97 on the pcb) I found the datarate being incorrect.
The standard setting for the system clocking in the SYS/BIOS dialog was 300MHz.
The timing seemed to be a result of a 350MHz system clock, so I adapted the UART settings to reach again 115.2kBaud.
Still I had mess on the pc-side of the uart, so I checked the system clock settings in the PLLCs and was very surprised when I found both PLLC in power down mode.
I do not program the PLLCs in my code, so (according to the technical reference) they should pass the 24MHz external clock to several peripherals.
But the UART seems to run from a clock source in the range of 350MHz (derived from the measurement with the scope).
Has anyone an idea what I overlooked?
Thanks!
