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TMDSEVM6657 Lite Evaluation Module

James Jolliffe
Intellectual 960 points

Other Parts Discussed in Thread: TMS320C6655, TMDSEVM6657, TMS320C6657

We are currently evaluating the TMS320C6655 device for our next product .  We started some preliminary bring-up and evaluation of DSP EVM over past couple of months and are now wanting to interconnect a Xilinx SP605 evaluation board to one of your TMDSEVM6657 Lite Evaluation Modules.  We have decided that the high speed interface that we believe makes the most since to stream data and keep overhead/cost down on FPGA side is PCIe but open to other suggestions.  Note: I have not used PCIe before in a design.  The TMDSEVM6657 support 1 or 2 lanes of PCIe over AMC edge card connector.  The  eInfoChip AMC to PCIe Adapter Brd  appears to support 4 lanes?  Basically we want to tap into a single PCIe lane on TMDSEVM6657 and connect to Xilinx SP605 which supports x1 PCIe lane edge connector.  The Xilinx FPGA (SP605 Eval Brd in this scenario) in actual system would be processing and streaming packetized data to single lane of TMDSEVM6657.   We need a way for prototype system using EVMs to interconnect Xilinx SP605 x1 PCIe lane to single lane of PCIe on AMC edge card connector of TMDSEVM6657.  I am trying to determine the best way to get there and if eInfoChip AMC to PCIe adapter card simplifies solution or if we should develop a data card.  Any suggestions would be greatly appreciated.

  • 0
    TI__Mastermind 42545 points

    Hi James,

    You have a number of questions so I'll try and answer as many as I can. As you pointed out, both the C6657 EVM and the Xilinx SP605 both have PCI express but the Xilinx card only supports an endpoint implementation using a single lane of Gen 1 PCIe. That equates to about 2Gb/sec of bandwidth on your PCIe interface. The C6657 can be configured as a root complex device but you would need the AMC to PCIe adapter board and a PCIe backplane. The backplane would have to have a PCIe slot for the root complex and slots for the endpoints. I don't have a source for that. 

    Are you attempting to model a final solution with this? If your goal is to connect these two boards in as simple a manner as possible, you many want to consider using the Ethernet ports. This reduces your bandwidth but the connection between the two platforms becomes a couple of Ethernet cables and a switch. 

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 960 points

    Bill,

    We want to show proof of concept with Evaluation Boards before developing our own boards.  We will have an internally developed  ADC Board that will pass High Speed differential data across to mezzanine connector on SP605.  The Xilinx device will do some processing of data and pass to TMS320C6655/57 in case of EVM.   We would like interconnect approach to be same as what we  plan to develop into our final internally developed board using the TMS32C6655.   Ethernet could be an option but in our final system topology we actually have the TMS320C6657 connected to our system presentation processor via Ethernet. The TMS320C6657 only has one Ethernet port and does not have an internal Ethernet switch.  I am trying to make use of best high speed connectivity option available with these devices that does not require significant overhead or costly IP in FPGA.    The main high speed serial options available as I see it are Serial Rapid I/O, Hyperlink, PCIe, and Ethernet .  The Universal Parallel Port could possibly be another option.  Due to overhead/cost reasons I do not believe TI Hyperlink or Serial Rapid I/O make since for FPGA  thus the reason I was thinking about PCIe??  In the case of PCIe, I was coming to conclusion that I would need some sort of AMC to PCIe daughter card to bridge connectivity between the 2 edge card interfaces.  I was thinking that it would be as simple as passing single lane diff pairs with ref clk but that does not appear to be the case based on root complex/backplane consideration you mentioned.  Remember I have not worked with PCIe before.   If that is the case, PCIe may not make since for a high speed device to device connection on the same board which I understand is not really what it was designed for?  I am not sure this has moved us any closer to a solution yet but I wanted you to understand our connectivity and what I am thinking. 

  • 0 in reply to James Jolliffe
    TI__Mastermind 42545 points

    Hi James,

    The PCIe can support a component-to-component connection on the same board without any problems. If the band width is sufficient for your application, this interface should work. The C6655/57 components can act as the root complex so it should be able to operate the connection to the Xilinx. Unfortunately, there isn't an easy method for proving your concept using the available evaluation modules. Another method you might consider is connecting the two boards using breakout cards. You can purchase a card that plugs into the AMC backplane which routes the PCIe and clock signals to SMA connectors. The same type of card can be purchased for the PCIe backplane connector on the Xilinx board. Then you can connect the two boards together using three pairs of coaxial cables. 

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 960 points

    HI Bill,

    This bandwidth is sufficient for our application.  As you noted the Xilinx on SP605 will be an endpoint configuration and the C6655/6657 will need to be configured as a root point/root complex.  I am moving forward with my original thought of generating a simple impedance matched daughter card that will plug onto 6657 AMC edge card finger.  I do not believe any of the available adapter cards really provide what we need.  Basically I plan to have a single lane R/.A PCB edge connector on one end of daughter card to interface to the SP605 EVM and a 170 pin R/A PCB edge connector on other end of daughter card to interface to 6657 DSP EVM AMC edge finger..  I currently am  planning to connect a single diff pair Transmit and Receive lane from DSP to single Gen1 lane available on SP605.  Basically 4 signals.  The other 2 signals would be diff pair PCIE_REF_CLK.  First I would like to confirm that this minimum subset of connections would be adequate between SP605 endpoint and 6657 root complex to properly negotiate a link and pass date successfully with both devices configured correctly.  If yes...my next question revolves around PCIE_REF_CLK.  After looking at this signal on DSP side, it appears that either a Ref clock input or internally generated 100MHz PCIE diff clock could be generated and passed to DSP PCIE diff clock input which would pass to PCIE Express Core.  It does not appear that internally generated PCIE clock on 6657 EVM could be passed to AMC edge connector and actually passed over to SP605 EVM...Did I miss something or is this correct.  On the SP605 end, it appears that the PCIE clk is also an input only as well which is then passed through a Jitter Attenuator.  Basically what I am saying is that both PCIE_Ref clocks to both boards appear to be inputs only and no way to pass PCIE clock from on board clock generator on DSP.  If this is the case, then I need to put a low jitter 100MHz clock generator to distribute to both EVMs on what I was hoping to be a fairly simple daughter card to interface between boards.     Please confirm and/or let me know what I am missing in my thought process.

  • 0 in reply to James Jolliffe
    TI__Mastermind 42545 points

    Hi James,

    I believe that your minimum configuration for PCIe connection is correct. As for the PCI ref clock, the PCIe standard allows the two ends to share a clock or use an independent clock if a spread spectrum clock is not used. It is common for the PCIe ref clock in PCs to be driven by a spread spectrum clock so most boards designed to plug into a PC will use the PCIe ref clock from the bus. Since we didn't use a spread spectrum clock on the EVM, we didn't put any circuitry on the board to drive the PCIe ref clock, but we did add the capability to accept a ref clock to cover that situation.

    It sounds like the SP605 is expecting to use the PCIe ref clock from the PCIe bus. Since we can't drive it from the EVM, you will have to include a clock on your simple backplane board. A 100MHz low jitter clock oscillator and a two output clock distribution part that supports the HCSL signal standard should be added to your design. Silicon Labs has a very good application note on PCIe reference clocks. I've included the link below.

    http://www.silabs.com/Support%20Documents/TechnicalDocs/PCIe-Clock-Source-Selection.pdf

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 960 points

    Hi Bill,

    In regards to clock,  the SP605 EVM is expecting a PCIe ref clock but it does also have a differential  SMA_REFCLK input which may be able to be routed to PCIe core on Xilinx side in place of refclck...TBD.  Since SMA connections on SP605 EVM, we could possibly use a stable  lab clock source to drive this PCIe device. On the 6657EVM side, you are already generating a PCIe clock (PCIECLKP/N) from CDCE62005RGZT which could also possibly be used in a SepRefClk architecture as long as jitter of clock on both ends of PCIe link is less than 300ppm.  Do you think it would be safe for this testing to just do a daughter card and pass TX/RX diff signals (basically 4 traces) and provide no refclk input to either EVM  and just use on board PCIe clk provided to each device as a SepRefClk.  If this has high risk, I can just add active clock circuitry to daughter card but If not needed to make PCIe link work then  could finalize my daughter card with 2 connectors and 4 traces with a ground plane on 2nd layer.  This would be simpler and PCB layout would be easier and faster.  If I add active clock circuitry, I need to add a separate supply source and probably would need 4 layers.  Your thoughts...

    James

    James