This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DDR3 Memory Wrap Around C6678

I'm testing my ddr3 module but i see a strange behaviour, a sort of Wrap Around of the memory.

Im testing the first 2 GB of my 8GB Kingston DDR3 Memory

Starting from the beginning of the Address (8x00000000) i'm able to write and read correctly up to 1GB of pseudo-random data without errors.
But if i try to write and read 2GB of data i see that the second GB is exactly the same of the first, as if after the address 8x40000000 the DSP start again writing from 8x00000000.

I still haven't changed the default setting for the MPAX for the DDR3 data memory space so i should be able to access to all the first 2 GB of the DDR3.

What could be the problem?

Thanks

  • Hi Henry,

    It could be a configuration issue. What Kingston memory are you using? If it is a module, what is the base device? What are your EBANK, IBANK, PAGESIZE and ROWSIZE settings?

    Regards, Bill

  • Hi Bill.

    I'm using a Kingston KVR16S11/8 With this settings:

    SDRAM_TYPE (fixed value = 0x3)
    IBANK_POS = 0
    DDR_TERM = 1 = RZQ/4
    DYN_ODT = 1 = RZQ/4
    SDRAM_DRIVE = 0 = RZQ/6
    CWL Cas Write Latency = 7
    NM = 0 = 64-bit bus width.
    CL Cas Latency = 10
    ROWSIZE = 7 => 16 row bits.
    IBANK = 3 => 8 bank SDRAM devices.
    EBANK = 0
    PAGESIZE = 2 => 1024-word page requiring 10 column address bits..

    I have some doubts about the EBANK setting:
    Using a value of of 0 i have the wrap around effect that i have described
    Using a value of 1 the inizialization of the DDR3 fail and i'm not able to write/read

  • Hi Henry,

    The EBANK setting is the reason that you are seeing the warp around behavior. If you look at table 2-6 of the KeyStone DDR3 Memory Controller User's Guide, you will see the logic address to SDRAM address mapping. The EBANK setting equates to an extra address bit in the center of the logical addressing. The SODIMM module that you are using is a dual-rank DIMM with devices installed on both sides of the board so EBANK should be equal to 1. 

    Note that the support for dual rank on the C6678 is limited. We do not support address mirroring on DIMM modules, which may be why the leveling is falling when you initialize with EBANK equal to 1. You'll have to check with Kingston to see if they have implemented their SODIMM with address mirroring. 

    Regards, Bill

  • Is there any way to use a dual-rank memory?
    In the datasheet is written that can be used external memory up to 8Gb so we've bought a 8GB module...

  • Dual-rank DIMMs are supported but only the type that do not use address mirroring as part of their routing. Address mirroring requires that the controller provides special modification to the SDRAM configuration written during the initialization of the devices. The controller in the KeyStone I devices does not support this capability. Unfortunately most commodity DIMM modules do use address mirror. As I said, you'll have to check with Kingston to see if the module you have is routed with or without address mirroring.  A little more information can be found at the following post.

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/333625/1163745.aspx#1163745

    Regards, Bill

  • Kingston havent still answered my question, but i believe this module uses mirroring.

    However, if i still want to use it, C6678 should be able to see it as a 4GB memory (Using EBANK = 0) instead of a 8BG memory right?
    But during my test, changing MPAX settings to use all aviable memory space, i'm able to use only a 1GB of space instead of the 4GB expected.
    1GB continuosly wrapped around...

  • there is no one who has ever experienced a similar problem?
    I've tryed different settings of IBANK_POS and different address remapping in the MPAX but i can only read and write 1 GB of RAM in an 8GB module.

    I know that for the lack of support for mirroring, i can not use them all, but I would expect to be able to use of at least 4GB...

  • Hi Henry,

    You should be able to access 4GB. I've checked your SDRAM settings and I don't see a problem. This may be an XMC setup issue. As an experiment, could you change the NM to 32bits and check the behavior of the memory? If the wrap address is cut in half, allowing access to only 512M of memory before the wrap occurs, than I believe it is a problem with the XMC. I'll ping the expert in XMC to get his opinion.

    Regards, Bill

  • Hi Bill, thanks for the answer.

    I've tried another test changing the NM setting to 32 bit... But now,even before changing MPAX, it seems i'm not even able to write and read correctly a single KB of data...

  • Hi Henry,

    Setting the NM to 32bit shouldn't cause the memory to fail. Do you still have the EBANK set to 0 for a single rank?

    Regards, Bill

  • Yes Bill, i've changed only the NM setting and EBANK is still 0.

  • I've to update this post

    The problem was in the code during the setup phase of the DDR3. Now we've fixed it and we're able to see the full 4GB window. Obviusly the 8GB is still not aviable due to the lack of address mirroring support