Examples Needed for Address Passing to ARM inline Assembly Code

Joey Lin

Intellectual 670 points

Dear Supporters:

My intention is to copy data from RAM to A8 Cortex L2 cache way via Preload Engine(PLE).

I am currently stuck on writing the virtual address to the PLE (3.2.64 c11). I wrote an api as below,

but the TI compiler has complained about its format. Could anyone provide examples for how to make

this work?

void Write_PLEStartAddress (UINT32 start_addr)
{
asm volatile(" mcr p15, #0, %0, c11, c5, #0" :: "r"(start_addr));
}

compiler error,

line 1266: error: expected a "("

line 1266: error: expected a ")"

My platform info: TMS320DM8148 (Vision-Mid)

600-MHz ARM® Cortex™-A8 RISC MPU

500-MHz C674x™ VLIW DSP

200-MHz M3-ISS/M3-HDVPSS

Thank you in advance,

Joey from Altek

over 11 years ago

0 Joey Lin over 11 years ago

Intellectual 670 points

I have just learnt that in TI SDK, there is a function written in assembly, named

memcpy_neon(dest, source, size);

This should provide me a hint for address passing. Could someone explain how does

the dest and source are passed in the assembly below?

.text
; .cpu cortex-a8
; .eabi_attribute 27, 3
; .fpu neon
; .eabi_attribute 20, 1
; .eabi_attribute 21, 1
; .eabi_attribute 23, 3
; .eabi_attribute 24, 1
; .eabi_attribute 25, 1
; .eabi_attribute 26, 2
; .eabi_attribute 30, 6
; .eabi_attribute 18, 4
; .file "memcpy.c"
.global memcpy_neon
.armfunc memcpy_neon
; .type memcpy_neon, %function
memcpy_neon:
cmp r2, #16
bge .L3
push {r0, lr}
subs r2, r2, #2
blt .L2
.L1:
ldrb r3, [r1], #1
ldrb lr, [r1], #1
subs r2, r2, #2
strb r3, [r0], #1
strb lr, [r0], #1
bge .L1
.L2:
cmp r2, #-1
ldreqb r3, [r1], #1
streqb r3, [r0], #1
pop {r0, pc}

.L3:
mov ip, r0
tst r0, #1
beq .L4
vld1.8 {d0[0]}, [r1]!
vst1.8 {d0[0]}, [ip]!
sub r2, r2, #1

.L4:
tst ip, #2
beq .L5
vld2.8 {d0[0], d1[0]}, [r1]!
vst2.8 {d0[0], d1[0]}, [ip]!
sub r2, r2, #2
.L5:
tst ip, #4
beq .L6
vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]!
vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [ip+32]!
sub r2, r2, #4
.L6:
tst ip, #8
beq .L7
vld1.8 {d0}, [r1]!
vst1.8 {d0}, [ip+64]!
sub r2, r2, #8
.L7:
subs r2, r2, #32
blt .L10
mov r3, #32
.L8:
vld1.8 {d0-d3}, [r1]!
cmp r3, #(320 - 32)
pld [r1, r3]
addle r3, r3, #32
sub r2, r2, #32
vst1.8 {d0-d3}, [ip+128]!
cmp r2, r3
bge .L8
cmp r2, #0
blt .L10
.L9:
vld1.8 {d0-d3}, [r1]!
subs r2, r2, #32
vst1.8 {d0-d3}, [ip+128]!
bge .L9
.L10:
tst r2, #16
beq .L11
vld1.8 {d0, d1}, [r1]!
vst1.8 {d0, d1}, [ip+128]!
.L11:
tst r2, #8
beq .L12
vld1.8 {d0}, [r1]!
vst1.8 {d0}, [ip+64]!
.L12:
tst r2, #4
beq .L13
vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]!
vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [ip+32]!
.L13:
tst r2, #2
beq .L14
vld2.8 {d0[0], d1[0]}, [r1]!
vst2.8 {d0[0], d1[0]}, [ip]!
.L14:
tst r2, #1
beq .L15
vld1.8 {d0[0]}, [r1]!
vst1.8 {d0[0]}, [ip]!
.L15:
bx lr

0 Joey Lin over 11 years ago in reply to Joey Lin

Intellectual 670 points

Dear supporters:

I supposed that the general purpose registers, r0, r1...,rN are used to pass arguments to

assembly function in my previous posting, so I write a simple *.asm file to write start address

to PLE c5 as below:

.global Write_PLEStartAddress

Write_PLEStartAddress:

mcr p15,#0,r0,c11,c5,#0

The buffer address of the passing argument is 0x80240158 (r0 shows correctly on CCS register view)

However, after I write the PLE start address and read back from registers by issuing the cmd,

mrc p15,#0,r0,c11,c5,#0

I got 0x80240178 or 0x8024016C, but never 0x80240158.

Could someone has any idea about why is this happening?

Best regards,

Joey from Altek

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Examples Needed for Address Passing to ARM inline Assembly Code