Keystone 2 EMAC - Fixed PHY

Rams,

Normally the application software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC.

You can find the EMAC details, how interfaced in EVMK2X board.  

The Ethernet PHY (PHY1 and PHY2) is connected to SoC EMAC0 & 1 to provide a copper interface and routed to a Gigabit RJ-45 connector (LAN1).

The EMAC2 & 3 of SoC is routed to Port0 & 1 of the AMC edge connector backplane interface.
In your design, Which EMAC are you going to interface with FPGA?

You can find the xilinx_axi_emac.c in the net driver part of uboot, it may help you.

The below wiki will help you for better understand of u-boot for EMAC
http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#U-Boot
http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#Ethernet_Driver
http://processors.wiki.ti.com/index.php/Linux_Core_CPSW_User's_Guide

Hello Pubesh,

Thanks for the clarification.  The ethernet module of keystone 2 EMAC0 and EMAC1 are interfaced with FPGA in PHYless mode.  In the u-boot, we try to initialize the EMAC by setting  the sgmii_link_type as SGMII_LINK_MAC_MAC_FORCED.  When we try to ping the fpga from the U-boot prompt, the CPU hangs.  

The CPU  hangs while accessing EMAC status registers.

What are the possible reasons which can hang the CPU while initializing EMAC?

Regards

Rams

,

Rams,

You have to carefully handle for the configuration of FPGA instead PHY.
This wiki pages may be you know already, will help you where you have to change the config for FPGA.
http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#Design.2FImplementation_Notes
http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#SGMII
http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#Enabling_MDIO

For debug through CCS:

http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Tools#Loading_and_Running_U-Boot_using_CCS

Hi,

I have a problem with the custom board.  The ethernet initialization sequence hangs in u-boot.  We tried disabling the ethernet initialization sequence and in the u-boot prompt tried to read the SGMII Status register, the CPU hangs.

1. We are unable to read the SGMII status register.  What are all the possible reasons for this?

2. We have checked the PASSCLK and SYS CLK and they are fine.

3. The SGMIIREFRES is not there whereas in EVM this is connected.  Is that mandatory to have SGMIIREFRES?  What is the use of this resistor?

Regards

Rams

Hi Pubesh,

Thanks for your response.  We tried to read the register from u-boot prompt.

We also tried to remove SGMIIREFRES from the EVM and see the same symptoms.

This confirms that the problem is with SGMIIREFRES resistor.

Thanks

Rams