• State Resolved
  • Locked Locked
  • Replies 16 replies
  • Subscribers 97 subscribers
  • Views 2749 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM335X GPMC connections

Jones A
Prodigy 110 points

Other Parts Discussed in Thread: AM3352

Hi ,

I am using AM3352 processor & connecting it to NOR flash of Multiplexed address data 16bit

Also following the TRM-GPMC Table 7.5 @ page 269 & 270 , i have to map NOR DEVICE A(16-26) with GPMC A(1-10) & A27

But the Pin mux utility tool showing IO SET violation on using GPMC A(1-10)_mux0 ; so i have used GPMC A(1-10)_MUX1

Please confirm why am getting IO SET VIOLATION on using MUX0 pins of GPMC A(1-10) and also confirm whether it is ok to have gpmc a(1-10)_mux1 {the left put option} ?

Thanks & Regards

Jones

  • 0
    TI__Guru**** 393215 points

    Hi Jones,

    You are getting an IO set violation because you are using something different from the predefined IO sets. You should use ONLY the predefined IO sets (or subsets from them). Any other combinations are not validated and should not be used. The set that does not give you a violation is OK.

    If you intend to boot from the NOR flash check section 26.1.7.2.2 in the AM335X TRM Rev. J about which pins should be used.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 110 points

    Hi Biser,

    Thanks for your reply & i am having 2 more queries,

    1. Does this AM3352 silicon is evaluated with a NOR FLASH of (256Mx8) or (128Mx16) ?.. Do we face any issues?

    2. Processor GPMC AD(0..15) is mapped to  NOR Flash...Would please sugeest the AM335X Processor Pins

        (BALL MAP) connecting for my NOR FLASH address pins A16-A26

    Thanks & Regards

    Jones

  • 0 in reply to Jones A
    TI__Guru**** 393215 points

    Jones A said:
    1. Does this AM3352 silicon is evaluated with a NOR FLASH of (256Mx8) or (128Mx16) ?.. Do we face any issues?

    A lot of customers have NOR flash in their designs, no specific issues I think.

    Jones A said:

    2. Processor GPMC AD(0..15) is mapped to  NOR Flash...Would please sugeest the AM335X Processor Pins (BALL MAP) connecting for my NOR FLASH address pins A16-A26

    Are you talking about an A/D multiplexed NOR flash or not? Do you want to boot from it?

  • 0 in reply to Biser Gatchev-XID
    Prodigy 110 points

    Hi Biser,

    Jones : Processor GPMC AD(0..15) is mapped to  NOR Flash...Would please sugeest the AM335X Processor Pins (BALL MAP) connecting for my NOR FLASH address pins A16-A26

    BISER : Are you talking about an A/D multiplexed NOR flash or not? Do you want to boot from it?

     

    Jones : Yes... I am using MULTIPLEXED ADDRESS DATA 16 BIT NOR FLASH (S70GL02GS11FHI010) & i wanna boot from it...

  • 0 in reply to Jones A
    TI__Guru**** 393215 points

    In this case read carefully section 26.1.7.2.2:

    "The list of device pins that are configured by the ROM in the case of NOR boot mode are as follows.
    Please note that all the pins might not be driven at boot time. The decision as to which pins need to be
    driven is done based on the type of NOR flash selected. The pins that are not listed below are not
    configured by the ROM code and are left at power-on defaults. Specifically, external logic is needed to
    isolate the upper address lines (A12–A27) of the NOR flash from the device pins and drive them low
    during non-muxed NOR boot. Similarly for Muxed NOR Boot, address lines A16 and above to the memory
    are not controlled by the ROM and need to be managed externally during boot to ensure proper
    addressing to the all memory signals."

    This means that you will need to pulldown A16 and higher addresses with external resistors during boot. One way to do this is by using a bus switch. SN74CBTLV16212GR is used on another EVM (DM8148 EVM expansion I/O board, page 28, link to schematics is http://www.mistralsolutions.com/pes-support/support-downloads/tmdxevm8148.html# ) - see it for example.

     

  • 0 in reply to Biser Gatchev-XID
    Prodigy 110 points

    Hi Biser,

    Thanks for your efforts

    Query 1 :

    I must need to use Multiplexed mode ; For that if am using NOR Flash A(16-26) to GPMC A1-A10 & A27 of mux0 (Balls - V14,U14, T14, ....V17) , i ended up with IO SET Violation error...... So i have to use the GPMC A1-A10,A27 of MUX1 (Balls R2,R3,R4,T1,T2,T3,T4).......As you have replied earlier do i strictly stick to GPMC_A0-A10,A27 MUX1 PINS?

    Query 2:

    If your answer to the above query is to use the GPMC A1-A10,A27 of MUX1 (Balls R2,R3,R4,T1,T2,T3,T4) for NOR Flash, Here i have problem that these pins are also used for SYSBOOT Option , where am using NOR/SDCARD/UART booting options......

    so its difficult to implement the external take care of a switch to pull down the Nor flash A16-22 signals , since its also sharing the SYSBOOT PINS

    Please suggest .....If am go ahead of using  GPMC A1-A10 & A27 of mux0 (Balls - V14,U14, T14, ....V17) , MY ISSUE IS SOLVED & also need to confirm there ,can i add up WEAK pull downs to the A16-A26 lines of nor flash instead of using a switch....

    kindly provide your feedbacks

    Regards

    Jones

  • 0 in reply to Jones A
    TI__Guru**** 393215 points

    You must not use IO sets that lead to violation errors. For the SYSBOOT pins you will need to place an analog switch towards the NOR address lines, that switches either pulldowns or processor addresses to the NOR. This switch should be controlled by a GPIO.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 110 points

    Thanks a lot Biser

    I have used switch to implement -

    PROCESSOR GPMC signals connecting SYSBOOT / NOR FLASH & also NOR FLASH A16-A26 address signals are pulled down

    Attached please find my implementation; I have used the NOR FLASH CHIP SELECT_L for switching logic

    Please confirm ; Thanks again

    Regards

    Jones

  • 0 in reply to Jones A
    TI__Guru**** 393215 points

    The CS signal won't do as switch control. During boot CS is active but the high addresses are not configured. You need a GPIO signal for that, that at reset release will put the switch in a state when high addresses will be pulled low. Then when MLO starts to execute, one of the first things it should do is configure the high addresses and control the GPIO so that address lines are switched to the NOR.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 110 points

    Hi Biser,

    As per your reply During BOOT (Sysboot before the MLO starts to execute) the Nor flash CS_N will be active

    In case if am using a GPIO signal , during BOOT (romcode) do this GPIO signal is HIGH since we cant access the ROM CODE ?

    My switching option is like, GPIO Should be high at BOOT and the Processor pins select the sysboot strapping / Nor flash a16-26 should be connected to pulldown

    Once MLO starts to execute, i should able to Access the  GPIO LOW connected to the switch.... & now the Processor pins will conect the NOR FLASH A16-26

    Please confirm wthere we can use the GPIO at ROM boot for my above switching options...

    Thanks &  Regards

    Jones

  • 0 in reply to Biser Gatchev-XID
    Prodigy 110 points

    Dear Biser,

    Can you provide any documents related to Booting & ROM Code executions

    Thanks & regards

    Jones

  • 0 in reply to Jones A
    TI__Guru**** 393215 points

    This is described in section 26 of the AM335X TRM Rev. J.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 110 points

    Thanks for your response!

     We have a query on the GPMC_CSn assertion timing.

     Initially after POR is released, the connections through the switch are

     1. AM335x GPMC_A16 to A22 signals to be connected to Sysboot 1..7

    2. NOR Flash A16 ..A26 Higher order address lines to be connected to GND

     Once the Sysboot detects the XIP boot setting, then we assume that the GPMC_CSn signal would be

    asserted (low), which would change the switch connections from NORFLash A16..A26 to AM335x A16..A26 pins. The sysboot resistor settings

    would be would be disconnected from the AM335x GPMC_A16 to A22 lines.

     

    Query 1  :  

    We would like to know more on the ROM code, when it would assert the Chip select after detecting the sysboot. As per your comments

    , "This is described in section 26 of the AM335X TRM Rev. J", we are unable to find this timing detail about the assertion of the GPMC_CSn

    signal.

     Query 2 : 

    Also, as advised by you, we cannot use the GPIO for controlling this switch because, during ROM code, we cannot access

    to GPIOs ( this is what we are assuming).

     We find the GPMC_CSn as the best control for this switching logic, if our assumption on the Csn timing that it would be asserted

    after XIP boot mode setting is detected is true.

     Query 3 : 

    Are there any other signals we could use like GPMC_Wait0 for controlling this switch ?

    Attached please find the switching implementation in schematics

    Thanks & Regards

    Jones

  • 0 in reply to Jones A
    TI__Guru**** 393215 points

    Q1: Sysboot pins are latched at reset release time, before the ROM code starts executing.

    Q2: What is important here is that the ROM code does not initialize the high addresses. They are left in their default state at reset release time. You need these addresses pulled low externally for initial code execution from NOR. All processor pins have a defined state at reset release time. This is given in Table 2-7 of the AM335X Datasheet Rev. F (see "Reset Release State/Mode" columns). This state will be preserved until user code modifies it.

    Q3: I suppose that this is a typo. GPMC_WAIT0 cannot be used for switch control, it's a processor input.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 110 points

    Hi Biser,

         Pls explain on how to control the switch during BOOT ROM code, since during Boot rom code, GPIOs cannot be used.

    Also, we would like to know when the GPMC_CSn would be asserted ? WE need the delay .

    Jones.

      

     

  • 0 in reply to Jones A
    TI__Guru**** 393215 points

    You don't control the switch during ROM code execution. You tie it for example to GPIO3_19 - this GPIO is low duing reset and remains low after reset is released (you can choose any free GPIO that's in the desired state during reset and after reset release - see Table 2-7 in the datasheet). Your sysboot pins are connected to AM335X at this time, and NOR address lines are pulled down. At some point ROM code jumps to execution of boot code from NOR flash. Somewhere during boot code execution pinmuxing is done for AM335X pins. As ROM code has configured only addresses up to A11 this pinmuxing has to happen inside the first 4kB of NOR flash code. You must ensure that your high addresses are pinmuxed as GPMC addresses. After that is done you set GPIO3_19 high and your AM335X high addresses are connected to the NOR flash. That's it, now you can address the entire NOR.

    If you don't understand this explanation I'm sorry, I cannot explain it better.