AM3352 starter kit TPS65910 PWRHOLD

Nikhil Tiwari

Other Parts Discussed in Thread: TPS65910, TPS65910A

Hi,

In the starter kit EVM the power hold pin of PMIC is connected to a pull up with VAUX33 supply. The user guide of TPS65910 (SWCU093C) has the timings in which the PWRHOLD should ramp when VRTC is stable. then other supplies ramp up. But when the board is powered on the VAUX33 supply will not be present and because of internal pull down the PWRHOLD will remain low.

In this case how the PMIC starts? is there any internal setting required for neglecting the PWRHOLD during the start up?

Thanks & Regards,

Nikhil

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Hi Nikhil,

See figure 4 in the TPS65910A datasheet.

0 Nikhil Tiwari over 12 years ago in reply to Biser Gatchev-XID

Intellectual 575 points

Hi Biser,

This diagram shows that when DEV_ON bit is set to 1 then the PWRHOLD is neglected. By default the datasheet shows that it is written as 0. So when is this bit set to 1 for starter kit EVM. Is it done using the EEPROM settings of PMIC?

Thanks & regards,

Nikhil

0 Biser Gatchev-XID over 12 years ago in reply to Nikhil Tiwari

TI__Guru**** 393215 points

The TPS65910A is programmed to work with AM335X. Boot mode 10b is used, which is EEPROM configuration.

0 Nikhil Tiwari over 12 years ago in reply to Biser Gatchev-XID

Intellectual 575 points

So in this configuration can i assume that this DEV_ON will be set to 1 if boot mode pins are 10? because the same is not provided in the User guide document SWCU093C.

Thanks & Regards,

Nikhil

0 Biser Gatchev-XID over 12 years ago in reply to Nikhil Tiwari

TI__Guru**** 393215 points

Look in the TPS65910 Datasheet, Table 6:

tdONPWHOLD: Delay to set high PWRHOLD signal or DEV_ON control bit after NRESPWRON released to keep on the supplies - 984 ms

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AM3352 starter kit TPS65910 PWRHOLD