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LVCMOS Pad Delay for the AM3352

Prasath Ayyamuthu
Prodigy 60 points

Other Parts Discussed in Thread: AM3352

I am planning use the SPI Master core (with 25 MHz SCK) in the AM3352. SPI Signals are routed into the FPGA and then forwarded to one of the SPI slave in the board. The FPGA doesn't have any SPI Master/Slave Interface, It just has Demux/Mux Logic to forward the SPI Transaction to one of the slave. With this Architecture, I am calculating the overall skew/delay for the SPI Transaction.

I need to calculate delay from the Internal Flop to Pin on the AM3352. During the timing budget estimation, 

I have found that AM3352 SPI Master Clock to Q  = 4.62 ns and  setuptime/holdtime = 3.02/4.7 ns. for the worst case.  I have calculated the SS/SIMO signals will be delayed by 4.62 ns + Pad delay From the FF to the Pin.

I need to find delay from the Internal Flop to Pin on the AM3352. I couldn't find the LVCMOS33 Pad Delay in the data sheet. Could any of you help me to find the IO Pad delay for the AM3352 ?

  • 0
    TI__Guru**** 393215 points

    There is no such information for the AM335X processor. All signal timings in the datasheet are given at pad boundary.

  • 0 in reply to Biser Gatchev-XID
    Prodigy 60 points

    Thanks for the Quick Response.  From the data sheet I see, tr Input signal rise time 8 ns,

    Does it mean the rise time is 8 ns at the Input Pad.?

    Based on your answer, At the Pad, The Delay between Clk and SIMO is 4.62 ns. Is that correct ?

    Also, What is the maximum Package skew/delay from the pad to the Pin for the AM335x Device?.

  • 0 in reply to Prasath Ayyamuthu
    TI__Guru**** 393215 points

    By pad I meant the processor pin. Internal timings are not publicly available.

  • 0
    Genius 3685 points

    Practical advice: FORGET IT!

    For SPI read cycles, you will have 2 times the delay of the FPGA, PLUS the delay of the SPI slave device, PLUS the setup time of the SPI Master. And the sum must be < 20ns, because the SPI master latches the data at the middle of the bit.


    I have had the same requirement as you. I have implemented a SPI master inside the FPGA, latching the incomming data at the end of the bit, and using an 8bit parallel interface to the CPU. 25MHz is no problem.


    If you have SPI read cycles and high speed, using the CPU SPI and multiplexing inside the FPGA will not work.

    You MIGHT have more luck if you use external analog switches for multiplexing.

    regards

    Wolfgang

  • 0 in reply to Wolfgang Muees1
    Prodigy 60 points

    There is a way to get this architecture working.  For the Read Transaction( Mode-0), The First data received by the master will be sampled (valid) on the second rising edge of the clock, first rising data should be ignored by the master due to round trip delay. This will cost additional clock. ie. It requires 17 clock's inorder to receive 16 Bit data.