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DM8168 Clocking and DDR3 Specifications

Mark Ackerson
Genius 10190 points

1.) Sysclk 8 derived from the DDR PLL is very confusing in the specification. Looking at Figure 1-71 it appears the sysclk8(OCP clock) should be configured for VCO/(MDIV1 * 2). Is this correct?

a. 1333MT/S (666 MHz), sysclk8=333Mhz.

b. 1600 MT/S (796.5 MHz), sysclk8=398.200 MHz

2.) In SPRS614E – Table 8-15 SysClk8 Frequencies seems to indicate that I need a TI8168 Device Speed rating of 4 in order to achieve a 1600 MT/S DDR3 given Sysclk8 only allows 380 MHz for blank and 2. However, this table is suspect, since I believe sysclk8 max is 400 Mhz not 450 Mhz.

Please advise.

Thanks,

Mark

  • 0
    TI__Genius 10190 points

    More questions from the documentation:

    1.)    Table 10-1 indicates the M3(Media Controller) has a 280 MHz for rating 2.  Table 1-73 sprugx8 indicates the Media Controller (M3 I believe) is sysclk4.  If this is correct, than which is the right number 280MHZ or 500 MHz?  If not sysclk4, which clock drives the M3?

    2.)    Table 10-1 indicates for speed rating 2, DDR3 can run 1600 MT/S.   Is sysclk8 depend on DDR clock? Perhaps I’m not understanding paragraph 1.10.3.1.2 of sprugx8. My guess is the CPU speed rating 2 can not support a 1600 MT/S since I believe sysclk8 = DDR2 clock/2.  Is this correct? If not, what should sysclk8 be set to?

    Please advise.

    Thanks,

    Mark

  • 0 in reply to Mark Ackerson
    TI__Guru*** 125430 points

    Mark Ackerson said:
    1.)    Table 10-1 indicates the M3(Media Controller) has a 280 MHz for rating 2.  Table 1-73 sprugx8 indicates the Media Controller (M3 I believe) is sysclk4.  If this is correct, than which is the right number 280MHZ or 500 MHz?  If not sysclk4, which clock drives the M3?

    There's a /2 inside the M3 subsystem.  In particular:

    • sysclk4=600 MHz --> 300 MHz M3
    • sysclk4=560 MHz --> 280 MHz M3
    • sysclk4=500 MHz --> 250 MHz M3

    So all of these numbers do actually match up once you know about the "secret" divider.

    Mark Ackerson said:
    2.)    Table 10-1 indicates for speed rating 2, DDR3 can run 1600 MT/S.   Is sysclk8 depend on DDR clock? Perhaps I’m not understanding paragraph 1.10.3.1.2 of sprugx8. My guess is the CPU speed rating 2 can not support a 1600 MT/S since I believe sysclk8 = DDR2 clock/2.  Is this correct? If not, what should sysclk8 be set to

    The DDR interface has multiple different clocks.  SYSCLK8 relates to the internal bus interface, i.e. it's used for the connection to the L3 interconnect (OCP).  There's a separate clock for the actual interface, i.e. what you would see on the actual pins.  I've marked up the clock diagram to help clarify:

  • 0
    TI__Guru*** 125430 points

    Both of these questions appear to be written under the assumption that SYSCLK8 is equivalent to the DDR external bus speed, which is not the case.  Hopefully in light of the previous post these answers will make more sense.

    Mark Ackerson said:

    1.) Sysclk 8 derived from the DDR PLL is very confusing in the specification. Looking at Figure 1-71 it appears the sysclk8(OCP clock) should be configured for VCO/(MDIV1 * 2). Is this correct?

    a. 1333MT/S (666 MHz), sysclk8=333Mhz.

    b. 1600 MT/S (796.5 MHz), sysclk8=398.200 MHz

    SYSCLK8 is the output of Flying Adder 3.  There's a fractional multiplier in there in addition to a divider (MDIV3).

    The number of MT/s is exactly the same speed as the VCO output.  In other words a 1600 MHz VCO output results in 1600 MT/s.  Related to the previous post that 1600 MHz clock goes through a /2 and that is the actual clock that is seen on the bus.

    Mark Ackerson said:
    2.) In SPRS614E – Table 8-15 SysClk8 Frequencies seems to indicate that I need a TI8168 Device Speed rating of 4 in order to achieve a 1600 MT/S DDR3 given Sysclk8 only allows 380 MHz for blank and 2. However, this table is suspect, since I believe sysclk8 max is 400 Mhz not 450 Mhz.

    Keep in mind that each 32-bit EMIF is fed by a 128-bit interface.  So even at "only" 380 MHz you have more than enough speed to stay ahead of the data.

  • 0
    TI__Mastermind 22946 points

    The DDR controller receives 2 clocks from the SoC – one the ocp_clk and the other m_clk. Both clocks are async w.r.t. each other. m_clk is the memory side clock which is dependent on the DDR speed and is always half the freq of the DDR clock.

    Sysclk8 feeds the ocp_clk, and therefore, does not dictate the DDR speed. The m_clk in the diagram is 400MHz which means DDR3-1600 is being used.

    Please use the formula as mentioned in PLL 8.3.4 section to calculate SYSCLK8, max frequency of which is 380 MHz for speed grade 2.

                                              fo = [ (N*K)/(FREQ*P*M)] * fr

  • 0 in reply to Manisha Agrawal
    Prodigy 40 points

    Thank you!!  (sysclk8) ocp_clk and (DDR clock/2)m_clk have no dependencies.  That was my question.