• State
  • Locked Locked
  • Replies 14 replies
  • Subscribers 98 subscribers
  • Views 1794 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DDR3 Setup for 1GB (2x512MB).

Dave Fish
Intellectual 360 points
Other Parts Discussed in Thread: DM385

I have a custom board that I'm trying to run u-boot.min.uart in the DDR3 RAM. I'm able to start up in SDRM without any trouble, but after I load the .uart file nothing is sent to the screen. 

I've run through the .out file for leveling, but I'm getting non convergent messages. 

I've been following the http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot instructions, but I'm not having much luck 

Here is my physical memory map

/**
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
#define PHYS_DRAM_1_SIZE 0x20000000 /* 512 MB */
#define PHYS_DRAM_2 0xA0000000 /* DRAM Bank #2 */
#define PHYS_DRAM_2_SIZE 0x20000000 /* 512 MB */

My DDR Defs

/*
* TI814X PG2.1 DMM LISA MAPPING
* 1G contiguous section with 128-byte interleaving
*/
#define PG2_1_DMM_LISA_MAP__0 0x0
#define PG2_1_DMM_LISA_MAP__1 0x0
#define PG2_1_DMM_LISA_MAP__2 0x0
#define PG2_1_DMM_LISA_MAP__3 0x80640300

/*
* DM385 DMM LISA MAPPING
* 1G contiguous section with no interleaving
*/
#define DDR3_DMM_LISA_MAP__0 0x0
#define DDR3_DMM_LISA_MAP__1 0x0
#define DDR3_DMM_LISA_MAP__2 0x0
#define DDR3_DMM_LISA_MAP__3 0x80600100

Other than those locations, and the leveling, is there something I'm missing? When I run the TI814x_ddr3.gel it seems to locate my DDR3 and init it...

HELP!

Thanks!

Dave

  • 0
    TI__Guru**** 170625 points

    Dave,

    Dave Fish said:
    I have a custom board that I'm trying to run u-boot.min.uart in the DDR3 RAM

    The u-boot.min.uart is the 1st stage bootloader (u-boot-MIN) and is loaded and running from within the internal L3 OCMC RAM, not from the external DDR3 RAM. This is configured from the ROM Code and can not be changed. Then the 2nd stage bootloader is loaded from the 1st stage bootloader prompt (TI-MIN#) to the DDR3 RAM.

    See the below wiki page for more info:

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_UBOOT_User_Guide#U-Boot

    TI814X/TI813X The ROM code loads the U-Boot-MIN image from the flash memory/SD card into OCMC RAM0. U-Boot-MIN does the basic configuration like setting up the clocks, initializing the necessary peripherals and then loads the U-Boot image from NAND,SPI/SD or UART.

    Best regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 360 points

    Thanks Pavel, 

    I have another question then...when I followed the instructions from this thread

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/245226/948918.aspx

    And changed the line in the Makefile:

    1) modify makefile line 3217:

    old->
            echo "TEXT_BASE = 0x80700000" >> $(obj)board/ti/ti8148/config.tmp; \

    new->
            echo "TEXT_BASE = 0x40310000" >> $(obj)board/ti/ti8148/config.tmp; \

    2) uncommnet the following line (line 42) in ti8148_evm.h

    //# define CONFIG_TI814X_CONFIG_DDR

    I did get the TI-MIN# prompt...why doesn't the default location work?

    Dave

  • 0 in reply to Dave Fish
    Intellectual 360 points

    By using the 0x40310000 I've been able to load into memory, and load flash, but once that's done, I can can't boot out of flash. 

    I ran the nboot command and it replied ** No boot devices **...why? How do I designate it a boot device. It know's it's there when I do nand info. 

    Thanks!

    Dave

  • 0 in reply to Dave Fish
    Intellectual 360 points

    Also, I've had to switch from an 16 bit NAND to an 8 bit. I changed the BTMODE like and can write and read to it...could that be the boot problem?

  • 0 in reply to Dave Fish
    Intellectual 360 points

    Got a bit further with the nboot

    TI8148_EVM#nboot 0 0

    Loading from nand0, offset 0x0

    But then it hangs...It doesn't seem to want to load the u-boot.min.nand file that's in flash...

  • 0 in reply to Dave Fish
    Intellectual 360 points

    I think I found the problem...now I need a solution!

    Once I reset the board, I can no longer access the DDR3. I have to go into the CCS and run the DDR3 gel file and set it all up...then I can access the RAM (And probably fix the rest of my problems)

    How do I get the DDR3 accessible across a reset?

  • 0 in reply to Dave Fish
    Intellectual 360 points

    Sorry for all the messages, but I'm making some progress! I've been able to flash both parts of the u-boot and they are still in the flash, but there is no where for the code to go!

    Thanks.

  • 0 in reply to Dave Fish
    Intellectual 360 points

    One more thing...I'm using u-boot version psp04.04.00.01 and the doc http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot

    Says I should be on 04.04.00.02...is it necessary for me to switch over?

  • 0 in reply to Dave Fish
    Intellectual 360 points

    One more more thing!

    To get the DDR3 running, I need to use the DM814x_PG2.x.gel file and run

    Centaurus2 System Init -> ALL_ADPLL_CLOCKS_ENABLE_API

    Centaurus DDR Configuration -> DDR3_EMIF0_EMIF1_Config

    Centaurus22_Core_CLKS_Configuration -> GPMC_Clkenable_API

    Or I can't run out of DDR3. 

    How do I get these to start up after a reset?

    Dave

  • 0 in reply to Dave Fish
    Intellectual 360 points

    Okay...

    I realized that the u-boot.min.nand should have been able to be loaded into internal memory and run, but I see nothing. Which means that the nand is probably not accessible to be loaded into memory. 

    Any ideas what could be stopping that?

    (Thanks for putting up with all the messages!)

  • 0 in reply to Dave Fish
    TI__Guru**** 170625 points

    Dave,

    So you have DM814x custom board and using CCS/JATG and EZSDK 5.05.02.00 / PSP 04.04.00.01, right?

    What is you final purpose? Is it to flash the NAND memory and boot the u-boot (1st stage and 2nd stage) (u-boot.min.nand and u-boot.bin) from the NAND flash?

    If yes, please have a look on the below E2E thread. We are discussing how to boot from NAND on the DM814x EVM, but for DM814x custom board should be similar.

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/333020.aspx

    Let me know if you have any specific questions.

    Best regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 360 points

    Pavel, 

    Yes it's a custom board with the versions you state above. 

    I've flashed the 1st uboot to nand, verified it in CCS. Yes, I'm try to boot from nand. The BTMODE pins are set correctly but I get nothing from serial on boot. 

    I'll look at the thread now. I have almost no access to any of the signals between the 8148 and the flash. The flash is an 8bit part, is that a problem? How can I tell if the 8148 is trying to load from flash? Anything in the CCS?

    Thanks for the help

    Dave

  • 0 in reply to Dave Fish
    Intellectual 360 points

    Pavel, 

    One other clue, I can't flash the 8bit Nand in CCS, I can however flash it after I start up in UART. 

    Dave

  • 0 in reply to Dave Fish
    TI__Guru**** 170625 points

    Dave,

    Dave Fish said:
    I've flashed the 1st uboot to nand, verified it in CCS. Yes, I'm try to boot from nand. The BTMODE pins are set correctly but I get nothing from serial on boot. 

    When you flash the NAND with the 1st stage uboot (u-boot.min.nand) you should be able to boot it and see the corresponding messages on the serial console. For example this is what I have:

    picocom v1.4

    port is        : /dev/ttyUSB0
    flowcontrol    : none
    baudrate is    : 115200
    parity is      : none
    databits are   : 8
    escape is      : C-a
    noinit is      : no
    noreset is     : no
    nolock is      : no
    send_cmd is    : sx -vv
    receive_cmd is : rz -vv

    Terminal ready


    U-Boot 2010.06-dirty (Mar 29 2013 - 17:44:47)

    TI8148-GP rev 2.1

    ARM clk: 600MHz
    DDR clk: 400MHz

    DRAM:  2 GiB
    NAND:  HW ECC BCH8 Selected
    256 MiB
    Using default environment

    The 2nd stage U-Boot will now be auto-loaded
    Please do not interrupt the countdown till TI8148_EVM prompt if 2nd stage is already flashed
    TI-MIN#

    The 1st stage uboot is running from the OCMC L3 RAM (0x40300000), not from the DDR3 RAM (0x80000000). Thus if you are not able to boot the 1st stage uboot, the problem should be not into the DDR3 RAM.

    Dave Fish said:
    The flash is an 8bit part, is that a problem?

    No, this is not a problem. The DM814x ROM Code supports both 8-bit and 16-bit NAND chips. See DM814x, Table 4-14. Supported NAND Devices, to check if your specific NAND chip is supported or not. Make sure also you configure the GPMC registers for your specific NAND, in example GPMC_CONFIG1_x[13:12] DEVICESIZE = 0x0 (8-bit device).

    Dave Fish said:
    How can I tell if the 8148 is trying to load from flash? Anything in the CCS?

    The easiest way to tell that the DM814x is trying to load from flash is using the serial console.

    Best regards,
    Pavel