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C6748 nand boot L2 ram usage.

Denny%20Yang99373
Expert 3805 points

Hi team,

One of customer use nand boot mode of C6748, they use aisgen tool to make the .ais file and set the entry point to 0x11800000, it will boot failed. But if set entry point to 0x11810000, everytings fine.

I have check spraat2f.pdf, nor lagceny boot will use the first 16KB of L2 ram, but haven't find any limted about nand boot mode.

Also I have check the pervious version spraat2a.pdf, it says:"Memory Usage: The bootloader uses 16 KB of DSP L2 RAM starting from 0x11800000 for multiple
purposes. This memory should not be used by any initialized section of the user application."  It seems the new version of this documents delete this.

So could you please help to confirm the nand boot requirement of L2ram?

Thanks!

BR,
Denny

  • 0
    TI__Guru** 116170 points

    I had a few things to clarify on this boot issue.Are you saying that the customer has modified the application as well as the AIS cfg to chnage the entry point. Entry point provided in the AIS Gen tools must match the entry point of the application that you are booting. The AISGen tool has the ability to parse a DSP boot image and figure out the entry point so it doesn`t have to be explicitly specified. Has the customer tried that.

     ROM uses some region of L1D to hold NAND structures and to define a 4K size memory buffer to temporarily store data read from a NAND page, it doesn`t seem to use any region in L2 memory.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    TI__Expert 3805 points

    Hi Rahul,

    The customer use a program_section pseudoinstruction to define _c_int00 address for entrypoint setting.
    Just change this section from 0x11800000 to 0x11810000, everything will goes well.

    BR,
    Denny

  • 0 in reply to Denny%20Yang99373
    TI__Guru** 116170 points

    Is it possible to share the .map file in both the above mentioned cases? Also please mention the silicon version that your customer is using.

  • 0 in reply to Rahul Prabhu
    TI__Mastermind 29082 points

    Rahul,

    From which revision silicon changed the temperary buffer to L1? in old revison bootloader app notes, the first 16KB L2 reserved for NAND boot also.