I was working on DM355 developing these days. I
tried DM35x_FlashAndBootUtils_1_50 on DM355 EVM. For nand chip K9WAG08U1A,
flash was erased and flashed well. After I changed it to Samsung K9F1208U0C, it
reported error message as follow:
Waiting for DONE...
DONE received. All bytes of image data received...
Target: Writing UBL to NAND flash
Target: Unprotecting blocks 0x00000001 through 0x00000018.
Target: Number of blocks needed for header and data: 0x0x00000002
Target: NAND block 0x00000001 is bad!!!
Target: NAND block 0x00000002 is bad!!!
Target: NAND block 0x00000003 is bad!!!
Target: NAND block 0x00000004 is bad!!!
Target: NAND block 0x00000005 is bad!!!
Target: NAND block 0x00000006 is bad!!!
Target: NAND block 0x00000007 is bad!!!
Target: NAND block 0x00000008 is bad!!!
Target: NAND block 0x00000009 is bad!!!
Target: NAND block 0x0000000A is bad!!!
Target: NAND block 0x0000000B is bad!!!
Target: NAND block 0x0000000C is bad!!!
Target: NAND block 0x0000000D is bad!!!
Target: NAND block 0x0000000E is bad!!!
Target: NAND block 0x0000000F is bad!!!
Target: NAND block 0x00000010 is bad!!!
Target: NAND block 0x00000011 is bad!!!
Target: NAND block 0x00000012 is bad!!!
Target: NAND block 0x00000013 is bad!!!
Target: NAND block 0x00000014 is bad!!!
Target: NAND block 0x00000015 is bad!!!
Target: NAND block 0x00000016 is bad!!!
Target: NAND block 0x00000017 is bad!!!
Target: NAND block 0x00000018 is bad!!!
Target: NAND block 0x00000019 is bad!!!
Target: No good blocks in allowed range!!!
Target: Writing failed!Starting UART Boot...
Target: BOOTUBL
I found following code in device_nand.h
/***********************************************************
* Global Macro Declarations *
***********************************************************/
#define DEVICE_NAND_DATA_OFFSET (0x00000000u)
#define DEVICE_NAND_ALE_OFFSET (0x00000008u)
#define DEVICE_NAND_CLE_OFFSET (0x00000010u)
#define DEVICE_NAND_TIMEOUT (10240)
#define DEVICE_NAND_MAX_BYTES_PER_OP (512) // Max Bytes per operation (EMIF IP constrained)
#define DEVICE_NAND_MAX_SPAREBYTES_PER_OP (16) // Max Spare Bytes per operation
#define DEVICE_NAND_MIN_SPAREBYTES_PER_OP (10) // Min Spare Bytes per operation (ECC operation constrained)
// Defines which NAND blocks the RBL will search in for a UBL image
#define DEVICE_NAND_RBL_SEARCH_START_BLOCK (1)
#define DEVICE_NAND_RBL_SEARCH_END_BLOCK (24)
// Defines which NAND blocks are valid for writing the APP data
#define DEVICE_NAND_UBL_SEARCH_START_BLOCK (25)
#define DEVICE_NAND_UBL_SEARCH_END_BLOCK (50)
I was wondering how to change these settings to use K9F1208U0C, any help
will be appreciated. Thank you!
Chip Features
K9WAG08U1A
Automatic Program and Erase
- Page Program : (2K + 64)Byte
- Block Erase : (128K + 4K)Byte
K9F1208U0C
Automatic Program and Erase
- Page Program : (512 + 16) x 8bits
- Block Erase : (16K + 512)Bytes
DEBUG info when uartboot
K9F1208U0C
Flash Base: 0x02000000
Bus Width: 0x00000001
Manufacture ID: 0x000000EC
Device ID: 0x00000076
Block count per device: 0x00001000
Page count per block: 0x00000020
Bytes per page: 0x00000200
Spare bytes per page: 0x00000010
Bytes per op: 0x00000200
Spare bytes per op: 0x00000010
Ops to r/w per page: 0x00000001
Column addr cycles: 0x00000001
Row addr cycles: 0x00000003
CS Offset: 0x00000000
*****************************
CHIP INFO
***************************
Device ID: 0x000000E3
Number of blocks: 0x00000200
Page per block: 0x00000010
Byte per page: 0x00000210
K9WAG08U1A
Flash Base: 0x02000000
Bus Width: 0x00000001
Manufacture ID: 0x000000EC
Device ID: 0x000000D3
Block count per device: 0x00001000
Page count per block: 0x00000040
Bytes per page: 0x00000800
Spare bytes per page: 0x00000040
Bytes per op: 0x00000200
Spare bytes per op: 0x00000010
Ops to r/w per page: 0x00000004
Column addr cycles: 0x00000002
Row addr cycles: 0x00000003
CS Offset: 0x00000000
*****************************
CHIP INFO
***************************
Device ID: 0x000000E3
Number of blocks: 0x00000200
Page per block: 0x00000010
Byte per page: 0x00000210