AM3352 with samsung K9F1G08U0D not working.

Hi Satish,

You need an external pullup resistor on GPMC_WAIT0. What software are you using?

Hi Biser,

we  are using AM335X_StarterWare_02_00_00_07 code.. GPMC_WAIT0 is connected to R/B of NAND flash.

Please find the below diagram..

Hi, 

The wait0 is Pulled up with a 10K Resistor.  Please find the Below image.

Are there 82Ohm serial resistors on the NAND signals? Try replacing them with zero Ohm.

Dear Sir,

We replaced the 82 Ohms with 0 Ohms. Even though its Not working. Please find the attached code for your reference.

Kindly do us favor.

With Regards

Umamageswaran. M

/**
 * \brief   This function selects the GPMC pins for NAND use. The GPMC pins
 *          are multiplexed with pins of other peripherals in the SoC
 *          
 * \return  TRUE/FALSE
 *
 * \note    This pin multiplexing depends on the profile in which the EVM
 *          is configured.
 */


unsigned int NANDPinMuxSetup(void)
{
 
    /* GPMC_AD0 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(0)) =
    ( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE_SHIFT);
    /* GPMC_AD1 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(1)) =
    ( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN_SHIFT)|
    ( 1 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE_SHIFT) ;
    /* GPMC_AD2 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) =
    ( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN_SHIFT)|
    ( 1 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE_SHIFT) ;
    /* GPMC_AD3 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(3)) =
    ( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN_SHIFT)|
    ( 1 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE_SHIFT) ;
    /* GPMC_AD4 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(4)) =
    ( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN_SHIFT)|
    ( 1 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE_SHIFT) ;
    /* GPMC_AD5 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(5)) =
    ( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN_SHIFT)|
    ( 1 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE_SHIFT) ;
    /* GPMC_AD6 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(6)) =
    ( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE_SHIFT) ;
    /* GPMC_AD7 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(7)) =
    ( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE_SHIFT) ;

    /* GPMC_WAIT0 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WAIT0) =
    ( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUDEN_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUTYPESEL_SHIFT)|
    ( 1 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RXACTIVE_SHIFT);

    /* GPMC_WPN */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WPN) =
    ( 7 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUDEN_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUTYPESEL_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RXACTIVE_SHIFT);

    /* GPMC_CS0 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(0)) =
    ( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUDEN_SHIFT)|
    ( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUTYPESEL_SHIFT)|
    ( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RXACTIVE_SHIFT);

    /* GPMC_ALE */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_ADVN_ALE) =
    ( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUDEN_SHIFT)  |
    ( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUTYPESEL_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RXACTIVE_SHIFT);

    /* GPMC_BE0N_CLE */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_BE0N_CLE) =
    ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN_SHIFT)  |
    ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE_SHIFT);

    /* GPMC_OEN_REN */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_OEN_REN) =
    ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE_SHIFT);

    /* GPMC_WEN */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WEN) =
    ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT)  |
    ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT);

    return TRUE;
}


Following Function is used to Read the NAND Flash ID:

/**
* \brief  Function to read the NAND Device ID.\n
*
*         This function reads the NAND device ID . It issues the
*         NAND read ID command and reads a 4-byte NAND device ID.\n
*
* \param  nandInfo      :  Pointer to structure which conatins controller and 
*                          device information.\n
*
* \return Updates the device id info in the nandDevInfo structure in nandInfo.\n
*/
 NandStatus_t NANDReadId(NandInfo_t *nandInfo)
{


	NandStatus_t retVal = NAND_STATUS_PASSED;
    unsigned int devId;

    /* Send the read ID command */
    NANDCommandWrite(nandInfo->cmdRegAddr, NAND_CMD_READID);

    UARTprintf("\n*********************LCD EM NAND Flash Read ID ********************\n");

    /* Write one cycle address with address as zero */
    NANDAddressWrite(nandInfo->addrRegAddr, 0x00);
    NANDDelay(10);

    NANDWaitUntilReady(nandInfo);

    /* Read the 4-byte device ID */
    nandInfo->manId = NANDDataReadByte(nandInfo->dataRegAddr);
    nandInfo->devId = NANDDataReadByte(nandInfo->dataRegAddr);
    
    UARTprintf("\nManf. Id: 0x%x DevId: 0x%x\n",nandInfo->manId,nandInfo->devId);

    if( (nandInfo->devId==0x00) || (nandInfo->devId==0xFF) )
    {
      retVal = NAND_STATUS_NOT_FOUND;
    }

    NANDDataReadByte(nandInfo->dataRegAddr);
    devId = NANDDataReadByte (nandInfo->dataRegAddr);

    /* Only try to detect device info from 4th ID byte if no valid  */
    /* values were given at initialization                          */
    if ( (nandInfo->pageSize == NAND_PAGESIZE_INVALID) ||
         (nandInfo->blkSize == NAND_BLOCKSIZE_INVALID) )
    {
        nandInfo->pageSize      = (NandPageSize_t) (1024 << (devId & 0x03));
        nandInfo->blkSize       = (NandBlockSize_t) ((64 << ((devId >> 4) & 0x3))*1024);
    }
    /* Only try to detect bus width info from 4th ID byte if no valid  */
    /* values were given at initialization                             */    
    if (nandInfo->busWidth == NAND_BUSWIDTH_INVALID)
    {
        if(devId >> 6 & 0x01)
        {
            nandInfo->busWidth = NAND_BUSWIDTH_16BIT;
        }
        else
        {
            nandInfo->busWidth = NAND_BUSWIDTH_8BIT;
        }
    }
    
    /* Calculate the pagesPerBlock */
    nandInfo->pagesPerBlk   = (nandInfo->blkSize/nandInfo->pageSize);
    
    return retVal;
}

uma mageswaran said:

Dear Sir,

We replaced the 82 Ohms with 0 Ohms. Even though its Not working. Please find the attached code for your reference.

Kindly do us favor.

With Regards

Umamageswaran. M

Fullscreen 2248.Source_Code.txt Download

/**
 * \brief   This function selects the GPMC pins for NAND use. The GPMC pins
 *          are multiplexed with pins of other peripherals in the SoC
 *          
 * \return  TRUE/FALSE
 *
 * \note    This pin multiplexing depends on the profile in which the EVM
 *          is configured.
 */


unsigned int NANDPinMuxSetup(void)
{
 
    /* GPMC_AD0 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(0)) =
    ( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE_SHIFT);
    /* GPMC_AD1 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(1)) =
    ( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN_SHIFT)|
    ( 1 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE_SHIFT) ;
    /* GPMC_AD2 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) =
    ( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN_SHIFT)|
    ( 1 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE_SHIFT) ;
    /* GPMC_AD3 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(3)) =
    ( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN_SHIFT)|
    ( 1 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE_SHIFT) ;
    /* GPMC_AD4 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(4)) =
    ( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN_SHIFT)|
    ( 1 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE_SHIFT) ;
    /* GPMC_AD5 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(5)) =
    ( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN_SHIFT)|
    ( 1 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE_SHIFT) ;
    /* GPMC_AD6 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(6)) =
    ( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE_SHIFT) ;
    /* GPMC_AD7 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(7)) =
    ( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE_SHIFT) ;

    /* GPMC_WAIT0 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WAIT0) =
    ( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUDEN_SHIFT) |
    ( 1 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUTYPESEL_SHIFT)|
    ( 1 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RXACTIVE_SHIFT);

    /* GPMC_WPN */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WPN) =
    ( 7 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUDEN_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUTYPESEL_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RXACTIVE_SHIFT);

    /* GPMC_CS0 */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(0)) =
    ( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUDEN_SHIFT)|
    ( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUTYPESEL_SHIFT)|
    ( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RXACTIVE_SHIFT);

    /* GPMC_ALE */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_ADVN_ALE) =
    ( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUDEN_SHIFT)  |
    ( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUTYPESEL_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RXACTIVE_SHIFT);

    /* GPMC_BE0N_CLE */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_BE0N_CLE) =
    ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN_SHIFT)  |
    ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE_SHIFT);

    /* GPMC_OEN_REN */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_OEN_REN) =
    ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE_SHIFT);

    /* GPMC_WEN */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WEN) =
    ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT)  |
    ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT) |
    ( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT);

    return TRUE;
}


Following Function is used to Read the NAND Flash ID:

/**
* \brief  Function to read the NAND Device ID.\n
*
*         This function reads the NAND device ID . It issues the
*         NAND read ID command and reads a 4-byte NAND device ID.\n
*
* \param  nandInfo      :  Pointer to structure which conatins controller and 
*                          device information.\n
*
* \return Updates the device id info in the nandDevInfo structure in nandInfo.\n
*/
 NandStatus_t NANDReadId(NandInfo_t *nandInfo)
{


	NandStatus_t retVal = NAND_STATUS_PASSED;
    unsigned int devId;

    /* Send the read ID command */
    NANDCommandWrite(nandInfo->cmdRegAddr, NAND_CMD_READID);

    UARTprintf("\n*********************LCD EM NAND Flash Read ID ********************\n");

    /* Write one cycle address with address as zero */
    NANDAddressWrite(nandInfo->addrRegAddr, 0x00);
    NANDDelay(10);

    NANDWaitUntilReady(nandInfo);

    /* Read the 4-byte device ID */
    nandInfo->manId = NANDDataReadByte(nandInfo->dataRegAddr);
    nandInfo->devId = NANDDataReadByte(nandInfo->dataRegAddr);
    
    UARTprintf("\nManf. Id: 0x%x DevId: 0x%x\n",nandInfo->manId,nandInfo->devId);

    if( (nandInfo->devId==0x00) || (nandInfo->devId==0xFF) )
    {
      retVal = NAND_STATUS_NOT_FOUND;
    }

    NANDDataReadByte(nandInfo->dataRegAddr);
    devId = NANDDataReadByte (nandInfo->dataRegAddr);

    /* Only try to detect device info from 4th ID byte if no valid  */
    /* values were given at initialization                          */
    if ( (nandInfo->pageSize == NAND_PAGESIZE_INVALID) ||
         (nandInfo->blkSize == NAND_BLOCKSIZE_INVALID) )
    {
        nandInfo->pageSize      = (NandPageSize_t) (1024 << (devId & 0x03));
        nandInfo->blkSize       = (NandBlockSize_t) ((64 << ((devId >> 4) & 0x3))*1024);
    }
    /* Only try to detect bus width info from 4th ID byte if no valid  */
    /* values were given at initialization                             */    
    if (nandInfo->busWidth == NAND_BUSWIDTH_INVALID)
    {
        if(devId >> 6 & 0x01)
        {
            nandInfo->busWidth = NAND_BUSWIDTH_16BIT;
        }
        else
        {
            nandInfo->busWidth = NAND_BUSWIDTH_8BIT;
        }
    }
    
    /* Calculate the pagesPerBlock */
    nandInfo->pagesPerBlk   = (nandInfo->blkSize/nandInfo->pageSize);
    
    return retVal;
}

Hi Biser,

Adding to the above comments from Uma :

We tried as per request of using 0 ohms instead of 82 ohms, still the behavior is same,

we found that CS is not enabled by GPMC controller when we tried to read ID of NAND flash chip from AM3352.

Please reply back asap.

Regards,

Satish

Probably the GPMC initialization is not correct. This forum only supports Linux. For Starterware questions please go to http://e2e.ti.com/support/embedded/starterware/f/790.aspx