Dear all,
I noticed that my computer vision algorithm was 10 time slower on DSP than on A9. So that, I tried to understand "why". When I measured the L1 cache access speed (reading many times at the same address with -O3 enabled). it appeared that the access time for L1 cache is something like 50 cycles, L2 cache access is about 200 cycles. I am not very familiar with C64T architecture so could you please confirm this rates? I was expecting something more like 10 cycles like A9.
Regards,
Kevin
