Hi,
I have two identical user boards. One board has
AM3359ZCZD72
29C8E2W GI
962 ZCZ
processor, and another board has
XAM3359AZCZ100
38C76TW GI
962A ZCZ.
Also, I have user application based on StarterWare 02.00.01.01. Data and Instruction cache is used In the application.
A shareable memory region is defined in the application:
REGION region_ddr_shareable = {MMU_PGTYPE_SECTION, 0x9e000000, 32,
MMU_MEMTYPE_NORMAL_SHAREABLE(MMU_CACHE_WT_NOWA,
MMU_CACHE_WB_WA),
MMU_REGION_NON_SECURE, MMU_AP_PRV_RW_USR_RW,
(unsigned int*) pageTable};
Data are saved into region_ddr_shareable during Interrupt Service Routine, and Main Loop procedure reads data from there.
The application works correctly on board with AM3359 processor.
On XAM3359, it seems that data are saved in Data Cache, but there is no coherency between cache and RAM.
If D-CACHE is turned off, (using only I-CACHE), application works correctly on both processors.
I tried to use MMU_CACHE_WT_NOWA for both inner and outer caches, but it didn't help.
Are there any differences between AM3359 and XAM3359A in scope of cache using?
What should me do to get coherent work of data cache on XAM3359?