AM335x connection between PRU_ICSS and PHY

RY9983

Hello,
AM335x PRU_ICSS is black box for user of Industrial communication.
I have found some differences between ICEv1.0B and ICEv2.1.
I would like to clarify how to connect to PRU_ICSS.

I am planning to use EthernetIP and Profinet.

a)
On ICEv1.0b, AM335x pr1_mii(0/1)_rxlink(U18, V2) pins are connected to LINK-LED of each PHYs.
On ICEv2.1, AM335x pr1_mii(0/1)_rxlink(U18, V2) pins are connected to SPEED-LED of each PHYs.
Which connection is correct?

b)
On ICEv1.0b, pr1_mii(0/1)_rxer(V3, V17) pins are connected to MII_RX_ERR of each PHYs. And, MII_COL is pulled down of each PHYs.
On ICEv2.1, pr1_mii(0/1)_rxer(V3, V17) pins are connected to MII_RX_ERR and MII_COL of each PHYs, which are ORed by logic.
Which connection is correct?

c)
On ICEv1.0b, MII_CRS of each PHYs is not used.
On ICEv2.1, PR1_MII(0/1)_CRS(V5, R6) pins are connected to MII_CRS of each PHYs.
Which connection is correct?

If you have connection guideline of PRU_ICSS, please let me know.

Best regards, RY

over 11 years ago

0 Biser Gatchev-XID over 11 years ago

TI__Guru**** 393215 points

Hi RY,

I would recommend that you adhere to ICE v2.1. This is the new revision, while v1.0 is getting quite old.

0 RY9983 over 11 years ago in reply to Biser Gatchev-XID

Guru 10570 points

Biser-san,

Thank you for your reply.
I think above difference is quite important, because it is regarding hardware design.

TI does not disclose detail of PRU_ICSS Firmware for using Industrial communication now.
But, we can not design without spec regarding hardware design.
Do you have any hardware design guideline for using Industrial communication?

Best regards, RY

0 Biser Gatchev-XID over 11 years ago in reply to RY9983

TI__Guru**** 393215 points

ICE v2.1 is the recommended reference design. You can also find the PRU reference manual here: https://github.com/beagleboard/am335x_pru_package

0 RY9983 over 11 years ago in reply to Biser Gatchev-XID

Guru 10570 points

Biser-san,
I understood your recommendation is ICEv2.1 reference design.
I have once more question.

On ICEv2.1,
pr1_mii0_rxer(V3) pin is connected to MII_RX_ERR and MII_COL of PHY(U3), which is ORed by logic.
pr1_mii0_col(T11) pin is NOT connected to PHY(U3).

pr1_mii1_rxer(V17) pin is connected to MII_RX_ERR and MII_COL of PHY(U2), which is ORed by logic.
pr1_mii1_col(T17) pin is connected to MII_COL of PHY(U2).

Question)
- Do I have to place the OR logic to operate correctly?
- Can I operate correctly by connect pr1_mii1_col(T17) to MII_COL of PHY(U2), instead of "OR logic"?

Best regards, RY

Processors

Processors forum

AM335x connection between PRU_ICSS and PHY