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Requester ID at Memory read C6678

kchakechk zakaria
Intellectual 460 points

Hello,

I'm using PCIe interface of C6678 DSP , for communication between two DSP "RC to EP" whit the IDT switch

But I still have the problem with Memory Read and I think it's a routing by ID problem, because I already passed the other transaction as Memory Write AND MSI interrupt.

Currently I have a question about configuring Request ID in each DSP I using TI provide MCSDK PCIe example project.

And I did not find the function that used to configure the requester ID field of the TLP header, I think maybe the problem just here.

 

Regards,

Zakaria

  • 0
    TI__Mastermind 28085 points

    Hi Zakaria,

    I have tested TI provide MCSDK PCIe example project (\ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\PCIE_exampleProject) it is working fine, Both C6678 EVMs are connected via Break Out Card (BOC). Refer the following document

    \ti\pdk_C6678_1_1_2_6\packages\ti\drv\pcie\example\sample\Readme.txt

    I think the issue in IDT switch configuration part, please get the support from IDT team and solve the issue.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 460 points

    Hi Ganapathi,

    Thank you for your answer, yes for me as Memory Read function very well with the BOC.

    But normally during generation of the transaction must be specified in the header Requested

    and this part is effected in the DSP, So my question is, how PCIEE in DSP will generate the Requester ID

    so that I can do the same configuration of RequesterID on the switch.

    Regards, Zakaria

  • 0 in reply to kchakechk zakaria
    TI__Mastermind 28085 points

    Hi Zakaria,

    PME Requester ID is only valid when the PME Status bit is Set.

    Refer section "3.7.10 Root Status and Control Register" on PCIE user guide (sprugs6d).

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 460 points

    Hi Ganapathi,

    Thank you for answer and for this information. so after set PME_STATUS where i can write the requester ID for each DSP because PME_REQ_ID fild is juste on read only

    Thanks,

    Zakaria

  • 0 in reply to kchakechk zakaria
    TI__Mastermind 28085 points

    Hi Zakaria,

    Yes, your understanding is correct.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 460 points

    Hi Ganapathi,

    Thanks . But I thing I don't understand because I don't know where exactly I should write RequesterID

    Thanks,

    Zakaria

  • 0 in reply to kchakechk zakaria
    TI__Mastermind 28085 points

    Hi Zakaria,

    PME_REQ_ID [Read Only] of the last PME Requester.

    The non-posted transactions comprise of a transaction layer packet (TLP) from the requester to completer. The completer, at a later time, sends a completion TLP to the requester. The completion TLP is used to inform the requester that the completer has received the request. In addition, the completion TLP also contains the data if the transaction was a read transaction. Non-posted write transactions contain the data in request TLP.

    For posted transactions, the request TLP is sent but there is no response TLP sent from the completer to the requester.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 460 points

    Hi Ganapathi,

    Thank you for your response, In order that you could understand my problem I am attaching a figure illustrating my settings. I would like to send a memory read from EP1 to RC. So I need to put in the packet request an address from where I want to read (this is not an issue), but I also need to give to the RC, the request IR of EP1 (which is in this case 03:0:0). My question is where I can configure the request ID in the MCSDK PCIe example project.

    Fig. Enumeration setup 

      Thanks again,

      Zakaria,

  • 0 in reply to kchakechk zakaria
    Intellectual 460 points

    Hello,

    there are some helps?

    Sincerely,

    Zakaria

  • 0 in reply to kchakechk zakaria
    TI__Mastermind 28085 points

    Hi Zakaria,

    The EP (Requester) tries to send memory read request to RC (Completer). The transaction layer in EP will create the TLP with request ID in its header automatically. But if EP needs to know its own Bus number/Device number/Function number ahead of time.

    Based on PCIe spec, before the first type 0 configuration write is performed to a function, it does not know the bus number and device number portion of its ID. While it remains in this state, a function is not permitted to initiate non-posted requests (such as memory read requests).

    Each time that the source bridge for a bus initiates a type 0 configuration write transaction, it supplies the targeted function with the bus number from its Secondary Bus Number register and the number of the device that the function resides within. The function is required to save this information for use in forming its IDs when it initiates a transaction as either a Requester or as a Completer. The information is not saved in program readable registers but rather in a function-specific manner.

    User has the enumeration software on RC/host to initialize the whole PCIe bus hierarchy (switches, EPs) and generate the configuration write transactions to each switches/EPs to assign the correct bus number/device number to them.

    Regarding to how to generate those configuration requests from C66x PCIe as RC, the user could use CFG_SETUP register and specify the target bus/device/function numbers for the target device (switch/EP) and try to read/write to remote device space in MMR (from offset 0x2000 in PCIe MMR space) to generate those configuration requests.

    TI not  provides this kind of RC/host enumeration software. User may need to create their own version in order to initialize the bus and assign the bus/device numbers to each device.

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 460 points

    Hi Ganapathi

    Thank you for your help and for giving me all the information, Now I understand these points:

    1- impossible to do the scenario where the EP generate Mrd with the code provided by TI.

    2- To realize this scenario, I need to configure CFG_SETUP and generate a configuration transaction type 0 at RC

    Can you confirm me these points?

    Can you help me about this subject later if I meet problems?

    Thanks again,

    Sincerely,

    Zakaria

  • 0 in reply to kchakechk zakaria
    TI__Mastermind 28085 points

    Hi Zakaria,

    Yes, you need to generate those configuration requests. 

    Thanks,