This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DDR3 leveling bit?

I'm designing with a C6657 DSP which will have 2 16 bit DDR3 RAMs attached so that the total data width is 32 bit, and have the following questions which I haven't been able to find answers to. I'm especially concerned about read and write levelling.

1)

Is it allowable to swap data bits within a byte?

2)

If the above answer is yes, must the exact same swapping also be applied to all byte groups (D0-7, D8-15, D16-23 and D24-32), or can they be different?