Context:
AM335x Industrial SDK running TI/BIOS and Starterware on a XAM3359ZCZ clocked at 600MHz
Assertion:
For CAN reception, IFxCMD UMASK OFF should be equivalent to UMASK ON with MASK set to 0xFFFFFFFF
When receiving message asynchronously with respect to outgoing transmission, this holds true.
IN my case, when receiving a reply to a transmission (with identical content from the same peer node), this assertion is FALSE, which I believe is not specification compliant.
Background: correct replies from peer node are not received by AM335x DCAN controller's own polling transmissions when UMASK is ON. Identical replies to identical, asynchronous polling transmissions from another test node ARE received as expected by the AM335x DCAN controller. AM3359x DCAN controller is observed to assert CAN_TXD in ACK time slot on ALL peer replies, indicating valid reception. Observed delay between rising edge of polling transmission's ACK and falling edge of reply message's SOF bit is 88uS (11 bit times). Transmit polling message ID is 0x3bc and reply is 0x3bd
Correct replies from peer node ARE received by AM335x DCAN controller's own polling transmissions when UMASK is OFF. The receiver works as expected in this configuration with no observed anomalies. This configuration, however, is unusable, as the receiver must accept all message IDs in this application.
Tested at 125kbps using BTR=0x1417, 0x1c4b, and 0x6f07
Receive object configuration code:
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while(DCANIFBusyStatusGet(CAN_BASE_ADD, DCAN_IF1_REG));
#if BROKEN
HWREG(CAN_BASE_ADD + DCAN_IFMCTL(DCAN_IF1_REG)) = DCAN_IFMCTL_UMASK | DCAN_IFMCTL_RXIE | (eob ? DCAN_END_OF_BLOCK_ENABLE : DCAN_END_OF_BLOCK_DISABLE);
#else // WORKS
HWREG(CAN_BASE_ADD + DCAN_IFMCTL(DCAN_IF1_REG)) = /*DCAN_IFMCTL_UMASK |*/ DCAN_IFMCTL_RXIE | (eob ? DCAN_END_OF_BLOCK_ENABLE : DCAN_END_OF_BLOCK_DISABLE);
#endif
DCAN_END_OF_BLOCK_DISABLE);
while(DCANIFBusyStatusGet(CAN_BASE_ADD, DCAN_IF1_REG));
HWREG(CAN_BASE_ADD + DCAN_IFMSK(DCAN_IF1_REG)) = 0xffffffffu;
while(DCANIFBusyStatusGet(CAN_BASE_ADD, DCAN_IF1_REG));
HWREG(CAN_BASE_ADD + DCAN_IFARB(DCAN_IF1_REG)) = (0x3bdu << 18u) | DCAN_11_BIT_ID | DCAN_IFARB_MSGVAL | DCAN_RX_DIR;
while(DCANIFBusyStatusGet(CAN_BASE_ADD, DCAN_IF1_REG));
HWREG(CAN_BASE_ADD + DCAN_IFCMD(DCAN_IF1_REG)) = DCAN_MSG_WRITE | DCAN_ACCESS_CTL_BITS | DCAN_ACCESS_MSK_BITS | DCAN_ACCESS_ARB_BITS | offset;
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when DCAN_IFMCTL_UMASK is commented out, the reception of synchronous reply messages succeeds. When DCAN_IFMCTL_UMASK is set, only asynchronous (yet otherwise identical) messages are received.In either case, the RXOK and TXOK bits in the status register go to ONE the same number of times (absent asynchronous messages). In other words, the synchronous reply is received properly by the hardware, but is being dropped in the acceptance filter, even though the message matches the acceptance filter exactly. But only when the acceptance mask is used. If the acceptance mask is enabled and set to various more liberal values, the message reception still fails.
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Delaying the response at the peer by 1.4msec (several message times) does not resolve the issue
Sending two identical peer replies results in a single message received by DCAN. The 1st reply begins at ACK+88usec, the second at ACK+700usec. DCAN CAN_TXD asserted in ACK timeslot for BOTH replies. Both replies are verified identical by a 3rd party observer.
Conclusion: the DCAN message acceptance filter state machine has an issue.
Am I missing something? Is there a workaround available for this issue?
