Other Parts Discussed in Thread: 66AK2H12
Hello,
When C66x/ARM reads/writes to EMIF16, it occurs twice 16bit accesses on EMIF16 on 66AK2H.
I would like to clarify:
When 32bit access via EMIF16 performed, which address occur first, lower address(LSB)? or upper address(MSB)?
There are four cases in 66AK2H12/06:
a) C66x read
LDW 0x30000000
1) 16bit read at 0x30000000 --> 16bit read at 0x30000002
2) 16bit read at 0x30000002 --> 16bit read at 0x30000000
Which is correct 1) or 2)?
b) C66x write
STW 0x30000000
1) 0x30000000 at 16bit write --> 16bit write at 0x30000002
2) 0x30000002 at 16bit write --> 16bit write at 0x30000000
Which is correct 1) or 2)?
c) CA15 read
LDR 0x30000000
1) 16bit read at 0x30000000 --> 16bit read at 0x30000002
2) 16bit read at 0x30000002 --> 16bit read at 0x30000000
Which is correct 1) or 2)?
d) CA15 write
STR 0x30000000
1) 0x30000000 at 16bit write --> 16bit write at 0x30000002
2) 0x30000002 at 16bit write --> 16bit write at 0x30000000
Which is correct 1) or 2)?
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My examination is following:
About case "b) C66x write"
It depends on LENDIAN pin state about C66x side access:
When I set LENDIAN high (means Little Endian):
- RCSR (0x21000a00) = 0x40000205 // Little endian
- SYSENDSTAT (0x02620710) = 1 // Little endian
- At result, I could see lower address(LSB) first on EMIF16 write access by oscilloscope.
When I set LENDIAN low (means Big Endian):
- RCSR (0x21000a00) = 0xC0000205 // Big endian
- SYSENDSTAT (0x02620710) = 0 // Big endian
- At result, I could see upper address(MSB) first on EMIF16 write access by oscilloscope.
About case "d) CA15 write"
It is not related to the LENDIAN pin configuration:
Both results were lower address(LSB) first by oscilloscope.
Best regards, RY
