Decrease McASP Transmit/Receive Clock

hakeen

Other Parts Discussed in Thread: OMAP-L137

I'm developing on OMAP-L137

Below are the McASP transmit setting.

/* TX */
mcasp->regs->XMASK = 0xffffffff; // No padding used
mcasp->regs->XFMT = 0x00008078; // MSB 16bit, 1-delay, no pad, CFGBus
mcasp->regs->AFSXCTL = 0x00000112; // 2TDM, 1bit Rising edge INTERNAL FS, word
mcasp->regs->ACLKXCTL = 0x000000AF; // ASYNC, Rising INTERNAL CLK, div-by-16
mcasp->regs->AHCLKXCTL = 0x00000000; // EXT CLK

According to SPRU041J C6000 McASP reference guide,

ACLKXCTL = 0x000000AF; => Bit 4-0 = 01111 = 15 => Divide by 16

The McASP transmit and receive clock run at 48KHz. So, I could execute "while ( ! ( MCASP1_SRCTL0 & 0x20 ) );"

48000 times per second.

When I set ACLKXCTL = 0x000000BF; , Bit 4-0 = 11111 = 31 => Divide by 32

The McASP transmit and receive clock run at 24KHz.

"while ( ! ( MCASP1_SRCTL0 & 0x20 ) );" could be executed 24000 times per second.

How could I set McASP transmit and receive clock as 16KHz?

The max value of ACLKXCTL CLKXDIV is 32. I can't set CLKXDIV as 48.

over 11 years ago

0 Sivaraj Kuppuraj over 11 years ago

TI__Mastermind 35645 points

Hi Hakeen,

Thanks for your post.

It is not possible to operate at very low McASP bit clock (ACLKX) like 16KHz etc. and there is some minimum criteria in setting the McASP's bit clock (ACLKX) and you cannot go beyond that. I mean, you cannot still reduce the McASP transmit/receive clock to go beyond Divide by 32(ACLKXCTL/ACLKRCTL). I think, there is transmit clock check & recovery circuit logic which continuously counts the no. of system clocks for every 32 high rate serial clock periods and the logic compares the count against a user-defined minimum allowable boundary (XMIN) and if any out-of-range condition occurs, it will automatically asserts the clock failure flag interrupt (XCLKFAIL). So, it is not possible to set clock divider (CLKXDV) to 48 and the max. limit is up to 32.

For more details, please refer section 3.6.6.2 in the McASP reference guide as below:

http://www.ti.com/lit/ug/spru041j/spru041j.pdf

Thanks & regards,

Sivaraj K

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0 hakeen over 11 years ago in reply to Sivaraj Kuppuraj

Intellectual 740 points

Hi Sivaraj

Thanks for the explain.

Max value of CLKXDIV of ACLKXCTL is 32.

So, the minimum McASP clock is 24KHz.

Is there other solution to lower down McASP clock? Change Hardware design? Change Oscillator?

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Decrease McASP Transmit/Receive Clock