• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 674 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6472 - clarification on EDMA maxwait and SRIO DMA maxwait

Eddie3909
Guru 10385 points

Other Parts Discussed in Thread: TMS320C6472

Hi

This relates to a post on CPU vs SRIO priority to L2.  But in this case, its EDMA vs SRIO priority to DDR.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/439/p/254392/1182136.aspx#1182136

I'd like to know what register defines the EDMA MAXWAIT when SRIO is set to a higher priority in PER_SET_CTRL relative to the EDMA priority in QUEPRI. From what I've read, the EMCSDMAARBE register defines the SDMA MAXWAIT for SDMA access which is used by both the SRIO and EDMA to access DDR. So how do you define different MAXWAITs? 

Or is it the case that if SRIO has higher priority than the EDMA, the MAXWAIT in EMCSDMAARBE applies to EDMA? And if reversed, the MAXWAIT then applies to SRIO?

Reference: Bandwidth management Architecture. See Chapter 6 (p144) of C64x plus Megamodule spru871k.pdf

Cheers2u

  • 0
    TI__Mastermind 20790 points

    You can follow the steps to enable the EDMA3CC completion. 

    • Enable the interrupt in the IER/IERH by writing into IESR/IESRH.
    • Ensure the EDMA3CC completion interrupt.
    • Set up the interrupt controller properly to receive the expected EDMA3 interrupt.

    You can choose to trigger completion when a TR leaves the EDMA3CC boundary, rather than wait for all of the data transfers to complete.
    Based on the setting of the EDMA3CC interrupt registers, the completion interrupt generation logic is responsible for generating EDMA3CC completion interrupts to the CPU.

    Here, each TC (transfer controller) has a programmed system priority. It is programmed through QUEPRI, that is
    implemented when multiple masters in the system are vying for the same endpoint.

    The priorities of transfer requests from the EDMA3 transfer controllers with respect to other masters within the system crossbar are programmed using the queue priority register(QUEPRI).

    QUEPRI programs the priority of the event queues.

    Find more details, refer the TMS320C6472/TMS320TCI648x DSP Enhanced DMA (EDMA3) Controller User's Guide
    http://www.ti.com/lit/ug/spru727e/spru727e.pdf
    http://www.ti.com/lit/an/spraay0a/spraay0a.pdf
    In addition that, this wiki article also help you.
    http://processors.wiki.ti.com/index.php/Programming_EDMA_without_EDMA3LLD_package
    http://processors.wiki.ti.com/index.php/EDMA_Background_Activity_for_OMAP-L1x/C674x/AM1x_Throughput_Measurements#External_Memory_Bandwidth_Usage

     

  • 0 in reply to Pubesh
    Guru 10385 points

    Hi

    My question is "I'd like to know what register defines the EDMA MAXWAIT when SRIO is set to a higher priority in PER_SET_CTRL relative to the EDMA priority in QUEPRI. "

    My question relates to the bandwidth management of the SCR bus when SRIO and EDMA are contending for it.

    Thanks

  • 0 in reply to Eddie3909
    TI__Expert 6815 points

    Hi Eddie,

    The MAXWAIT value applies to all SDMA transactions i.e. you cannot further program it granularly for EDMA v/s SRIO v/s some other master. QUEPRI is the only place you can really affect the EDMA priority relative to other SoC masters at the SCR level.

    Also note that SDMA impacts transactions to L1D, L2, and EMC resources and is not used to access DDR. The DDR2 controller is connected directly to the SCR.

  • 0 in reply to Aditya
    Guru 10385 points

    Hi Aditya

    Re: 

    Aditya said:
    Also note that SDMA impacts transactions to L1D, L2, and EMC resources and is not used to access DDR. The DDR2 controller is connected directly to the SCR.

    Wow, did I have that wrong then.

    So if I set the SRIO priority in PER_SET_CTRL higher than the EDMA priority in QUEPRI, what register do I use to set the EDMA's MAXWAIT?

    And if I set the SRIO priority in PER_SET_CTRL lower than the EDMA priority in QUEPRI, what register do I use to set the SRIO's MAXWAIT?

    Thanks (I really appreciate your help)