OMAP 3530 Setting up mailbox interrupt on DSP side

Hi,

I've been debugging this issue for hours and can't figure out what goes wrong.

I'm not using DSP/BIOS, I developed a module to load and run DSP code from Linux (ARM side).

Here is how I enable and set up Mailbox interrupt:

1.Mailbox set up, I believe there is no problem, since I can see Mailbox_IRQSTATUS_1 is changed every time I let ARM write to the DSP mailbox.

2. DSP side interrupt set up is as follows:

CLEAR_BIT(CSR,0);	//GIE, global interrupt disable

SET_BIT(REG(WUGEN_BASE+MEVTCLR(0)),10);	
//WUGEN allow device interrupt,Mailbox is IRQ[10] for DSP


REG(IC_BASE+EVTMASK(1))=0xFF7FFFFF;
REG(IC_BASE+INTMUX(1)) = REG(IC_BASE+INTMUX(1))&(0xFFFFFF00)|(0x01); 
//EVENT 55->EVT1 Mailbox map to INT4

	ISTP =(unsigned int)vectorTable;
	ICR=0xFFF0;
	IER = 0x0000;
	SET_BIT(IER,4); //IER,enable INT4
	SET_BIT(IER,1); //NMIE
	SET_BIT(CSR,0);	//GIE, global interrupt enable

3. #define INTMUX(j) 0x104+(0x4*j)

INTMUX(j) is a bit unclear from the TRM,

4. I've manually test the Interrupt service routine, the Interrupt Vector Table I believe is set up correctly, I can see the ISR gets called and return just fine.

5. However, when I run my program, 

EVT FLAG0: a

EVT FLAG1: 80 0000

IFR is always 0.

And it seems that I wasn't able to clear these event flags, and even worse is that IFR stays at 0.

6.If I change INTMUX to use single event, (rest settings don't change)

REG(IC_BASE+INTMUX(1)) = REG(IC_BASE+INTMUX(1))&(0xFFFFFF00)|(0x37);

I get IFR=100, which does not make sense to me. I register for INT4, I expect IFR=0x10;

I found another related post, but no one answers it.http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/t/110169.aspx

Yesterday I got it work for a couple of times but the ISR not return properly, but now I cannot get interrupt fired anymore.....Please help with this issue,

Thanks,

Airie