DM6437 EVM: full duplex communication between McBSPs as SPI Master and Slave

Naresh Patel1

8765.mcbsp.zip

Hello,

I am using DM6437 EVM.

I have externally connected pins (transmit and receives) between McBSP0 and McBSP1 as per SPRU943c.

I have successfully communicate between McBSP0 (as SPI Master) and McBSP1( as SPI Slave) in half duplex mode i.e means data transfer from SPI master to SPI slave.

However I could not able to do data transfer in Full duplex mode i.e McBSP1 (as a SPI slave) not able to transfer data to McBSP0 (as a SPI master). (data transfer from Slave to master)

Is it possible to do full duplex communication if we configure McBSPs as Master and Slave on DM6437?

I have gone through SPRU943 but can't find anything for full duplex communication between McBSPs if configure as master and slave.

I have attached my testing code here with. Please do the needful ASAP.

Regards,

Naresh

over 11 years ago

0 Sivaraj Kuppuraj over 11 years ago

TI__Mastermind 35645 points

Hi Naresh,

Thanks for your post.

As the DM6437 in SPI slave mode, not able to transfer data to SPI master because the maximum SPI data rate is dependent on the SPI master. As long as the DM6437 McBSP CLKG is 8 times faster than the CLKX/CLKR (from the SPI master) the DM6437 McBSP should be able to handle the data sent from the SPI master.

Since the DM6437 McBSP is running on SYSCLK3 which is divided by 6 from the DM6437 clock, if the DM6437 is operated at 300Mhz, for example, the slave McBSP SPI should work with the master clock of 6Mhz which requires the McBSP CLKG of 48-50Mhz. You can achieve this by select the SRG clock source as the McBSP internal clock and setting the CLKGDV =0. If it works, you should be able get a throughput of 6Mbps.

With the above data points, you must able to validate the data throughput which is required for the data transfer to happen in Full duplex mode from SPI slave to SPI master would be feasible or not.

May be, you could check the below E2E post which has the test code but it is written with old CSL drivers unfortunately:

http://e2e.ti.com/support/embedded/tirtos/f/355/t/97315.aspx

Thanks & regards,

Sivaraj K

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Please click the Verify Answer button on this post if it answers your question.
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0 Naresh Patel1 over 11 years ago in reply to Sivaraj Kuppuraj

Intellectual 330 points

Hi Shivraj,

Thank you for your replay.

Unfortunately, you haven't answer my question.

I have configured Mcbsp0 as Master and McBSP1 as a slave in clock stop mode as per the SPRU943c.

I am able to send data from McBSP0 to McBSP1 successfully but I am not able to send data from McBSP1 to McBSP0.

I have simple Question.

Is it possible to send data from McBSP1(SPI slave) to McBSP0 (spi master)??????

if yes then how?????

Regards,

Naresh

P.S. Here I have pasted the code and this are the freq config values.

EVM DM6437 clock freq 594Mhz,

MCBSP freq 99MHz,

SPI Master (Mcbsp0) clock freq 1 Mhz, clock divider value 99.

SPI Slave (Mcbsp1) clock freq 8.25 Mhz, clock divider value 12.

int main (void)

{
//enable mcbsp0 in power and sleep controller
device_init();

//setup mcbsp registers and start mcbsp running
init_mcbsp();

//test loopback, returns 0 for pass and 1 for fail
return(test_mcbsp());
}

void init_mcbsp(void)
{
int i;
//serial port control register SPCR
CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_RRST,DISABLE); //receiver enable
CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_XRST,DISABLE); //transmitter enable
CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_GRST,RESET); //SRGR out of reset
CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_FRST,RESET); //enable frame sync

//mcbsp0Regs->SPCR = CSL_FMKT(MCBSP_SPCR_DLB,ENABLE); //enable loopback mode
mcbsp0Regs->SPCR = CSL_FMKT(MCBSP_SPCR_CLKSTP,DELAY); //enable clk stop mode with NODELEY or DELAY

// receive control register
//mcbsp0Regs->RCR = CSL_FMKT(MCBSP_RCR_RWDLEN1,32BIT) //receive word 32bit
// | CSL_FMK(MCBSP_RCR_RFRLEN1,NUM_WORDS); //1st Phase frame length RFRLEN1
//CSL_FINST(mcbsp0Regs->RCR, MCBSP_RCR_RDATDLY,1BIT); //receive data delay 1bit

//transmit control register
mcbsp0Regs->XCR = CSL_FMKT(MCBSP_XCR_XWDLEN1,32BIT) //trans word 32bit
|CSL_FMK(MCBSP_XCR_XFRLEN1,0); //1st Phase frame length XFRLEN1
CSL_FINST(mcbsp0Regs->XCR, MCBSP_XCR_XDATDLY,1BIT); //trans data delay 1bit

//sample rate generator SRGR
mcbsp0Regs->SRGR = CSL_FMKT(MCBSP_SRGR_CLKSM,INTERNAL) //internal clock, defualt CLKG
//| CSL_FMKT(MCBSP_SRGR_FSGM,DXR2XSR) //(FSGM = DXR2XSR or FSG, FSX is generated only when DXR to XSR copy)
//| CSL_FMKT(MCBSP_SRGR_GSYNC,FREE) //(GSYNC = FREE or SYNC, Sample rate generator is free running, defualt FREE)
//| CSL_FMKT(MCBSP_SRGR_CLKSP,RISING) //(CLKSP = RISING or FALLING, CLKS polarity is used only when clks are external, defualt RISING )
//| CSL_FMK(MCBSP_SRGR_FPER,63) //frame period
//| CSL_FMK(MCBSP_SRGR_FWID,31) //frame width
| CSL_FMK(MCBSP_SRGR_CLKGDV,99); //clock divider value

mcbsp0Regs->SRGR |= (0 << 31); // (GSYNC = 0, Sample rate generator is free running)
mcbsp0Regs->SRGR |= (0 << 30); // (CLKSP = 0, CLKS polarity is used only when clks are external)
mcbsp0Regs->SRGR |= (0 << 28); // (FSGM = 0, FSX is generated only when DXR to XSR copy)

//pin control register
mcbsp0Regs->PCR = CSL_FMKT(MCBSP_PCR_FSXM, INTERNAL) //internal frame sync defualt EXTERNAL
//| CSL_FMKT(MCBSP_PCR_FSRM,EXTERNAL) //internal fram sync defualt EXTERNAL
//| CSL_FMKT(MCBSP_PCR_CLKRM,INPUT) //internal fram sync defualt INPUT
| CSL_FMKT(MCBSP_PCR_CLKXM, OUTPUT) //trans clock mode
| CSL_FMKT(MCBSP_PCR_FSXP, ACTIVELOW) //ACTIVELOW or ACTIVEHIGH, FSX polarity is used only when clks are external, defualt RISING
| CSL_FMKT(MCBSP_PCR_CLKXP, RISING) //RISING or FALLING, CLKS polarity is used only when clks are external, defualt RISING
| CSL_FMKT(MCBSP_PCR_SCLKME, NO); //sample clock mode selection bit defualt NO, else BCLK to set 1

// McBSP 1 config
#if 1
//serial port control register SPCR

CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_RRST,DISABLE); //receiver enable
CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_XRST,DISABLE); //transmitter enable
CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_GRST,RESET); //SRGR out of reset
CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_FRST,RESET); //enable frame sync

//mcbsp1Regs->SPCR = CSL_FMKT(MCBSP_SPCR_DLB,ENABLE); //enable loopback mode
mcbsp1Regs->SPCR = CSL_FMKT(MCBSP_SPCR_CLKSTP,DELAY); //enable clk stop mode with NODELEY or DELAY

// receive control register
mcbsp1Regs->RCR = CSL_FMKT(MCBSP_RCR_RWDLEN1,32BIT) //receive word 32bit
| CSL_FMK(MCBSP_RCR_RFRLEN1,0); //1st Phase frame length RFRLEN1
CSL_FINST(mcbsp1Regs->RCR, MCBSP_RCR_RDATDLY,0BIT); //receive data delay 1bit

//transmit control register
//mcbsp1Regs->XCR = CSL_FMKT(MCBSP_XCR_XWDLEN1,32BIT) //trans word 32bit
// | CSL_FMK(MCBSP_XCR_XFRLEN1,NUM_WORDS); //1st Phase frame length XFRLEN1
//CSL_FINST(mcbsp1Regs->XCR, MCBSP_XCR_XDATDLY, 0BIT); //trans data delay 1bit

//sample rate generator SRGR
mcbsp1Regs->SRGR = CSL_FMKT(MCBSP_SRGR_CLKSM,INTERNAL) //internal clock, defualt CLKG
//| CSL_FMK(MCBSP_SRGR_FSGM,DXR2XSR) //(FSGM = DXR2XSR or FSG, FSX is generated only when DXR to XSR copy)
//| CSL_FMK(MCBSP_SRGR_GSYNC,FREE) //(GSYNC = FREE or SYNC, Sample rate generator is free running, defualt FREE)
//| CSL_FMK(MCBSP_SRGR_CLKSP,RISING) //(CLKSP = RISING or FALLING, CLKS polarity is used only when clks are external, defualt RISING )
//| CSL_FMK(MCBSP_SRGR_FPER,63) //frame period
//| CSL_FMK(MCBSP_SRGR_FWID,31) //frame width
| CSL_FMK(MCBSP_SRGR_CLKGDV,12); //clock divider value

//pin control register
mcbsp1Regs->PCR = CSL_FMKT(MCBSP_PCR_FSXM, EXTERNAL) //internal frame sync defualt EXTERNAL
//| CSL_FMKT(MCBSP_PCR_FSRM,EXTERNAL) //internal fram sync defualt EXTERNAL
//| CSL_FMKT(MCBSP_PCR_CLKRM,INPUT) //internal fram sync defualt INPUT
| CSL_FMKT(MCBSP_PCR_CLKXM, INPUT) //trans clock mode
| CSL_FMKT(MCBSP_PCR_FSXP, ACTIVELOW) //ACTIVELOW or ACTIVEHIGH, FSX polarity is used only when clks are external, defualt RISING
| CSL_FMKT(MCBSP_PCR_CLKXP, RISING) //RISING or FALLING, CLKS polarity is used only when clks are external, defualt RISING
| CSL_FMKT(MCBSP_PCR_SCLKME, NO); //sample clock mode selection bit defualt NO, else BCLK to set 1

CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_GRST,CLKG); //SRGR out of reset
for ( i = 0; i < 200; i++ ) { i++; }
CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_RRST,ENABLE); //receiver enable
CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_XRST,ENABLE); //transmitter enable
for ( i = 0; i < 200; i++ ) { i++; }
CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_FRST,FSG); //enable frame sync
#endif
//start the mcbsp running
CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_GRST,CLKG); //SRGR out of reset
for ( i = 0; i < 200; i++ ) { i++; }
CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_RRST,ENABLE); //receiver enable
CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_XRST,ENABLE); //transmitter enable
for ( i = 0; i < 200; i++ ) { i++; }
CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_FRST,FSG); //enable frame sync

}

int test_mcbsp(void)
{
int i;

printf("\nTesting mcbsp loopback SDK\n\n");

// mcbsp 0 transmit and mcbsp 1 receive
for(i=0;i<NUM_WORDS;i++)
{
trans_val[i] = transBuff[i];
//poll transmitter ready
while(CSL_FEXT(mcbsp0Regs->SPCR,MCBSP_SPCR_XRDY)
!= CSL_MCBSP_SPCR_XRDY_YES);

//write to transmit register
mcbsp0Regs->DXR = trans_val[i];

//poll receiver is ready
while(CSL_FEXT(mcbsp1Regs->SPCR,MCBSP_SPCR_RRDY) != CSL_MCBSP_SPCR_RRDY_YES);
rec_val[i] = mcbsp1Regs->DRR;

}

//check results
for(i=0;i<NUM_WORDS;i++)
{
if(trans_val[i]==rec_val[i])
printf("transmit: 0x%x receive: 0x%x\n",trans_val[i],rec_val[i]);
else
{
printf(" error\n");
printf("\nMCBSP Loopback Test: FAILED\n");
printf("transmit: 0x%x receive: 0x%x\n",trans_val[i],rec_val[i]);
return(1);
}
}

// mcbsp 1 transmit and mcbsp 0 receive
for(i=0;i<NUM_WORDS;i++)
{
rec_val0[i] = 0;
trans_val[i] = transBuff[i];
//poll transmitter ready
while(CSL_FEXT(mcbsp1Regs->SPCR,MCBSP_SPCR_XRDY) != CSL_MCBSP_SPCR_XRDY_YES);

//write to transmit register
mcbsp1Regs->DXR = trans_val[i];
printf("transmit: 0x%x\n",trans_val[i]);
//poll receiver is ready
while(CSL_FEXT(mcbsp0Regs->SPCR,MCBSP_SPCR_RRDY) != CSL_MCBSP_SPCR_RRDY_YES);
rec_val0[i] = mcbsp0Regs->DRR;
printf(" receive: 0x%x\n",rec_val0[i]);

//while(intFlag0 != 0);
// intFlag0 = 1;

}

//check results
for(i=0;i<NUM_WORDS;i++)
{
if(trans_val[i]==rec_val0[i])
printf("transmit: 0%x receive: 0x%x\n",trans_val[i],rec_val0[i]);
else
{
printf(" error\n");
printf("\nMCBSP Loopback Test: FAILED\n");
printf("transmit: 0x%x receive: 0x%x\n",trans_val[i],rec_val0[i]);
return(1);
}
}

printf("\nMCBSP Loopback Test: PASSED\n");

return(0);
}

Fullscreen 7433.Mcbsp_example.c Download

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006, 2007
 *
 *   Use of this software is controlled by the terms and conditions found
 *   in the license agreement under which this software has been supplied.
 *  ============================================================================
 */

/** ============================================================================
 *   @brief A simple example to demonstrate CSL 3.x MCBSP register layer usage.
 *
 *   @file  mcbsp_example.c
 *
 *   <b> Example Description </b>
 *   @verbatim
     This example configures MCBSP0 in 32 bit loopback mode and uses software 
     polling to transmit and receive 32bit words. Four 32 bit words are 
     transmitted and received and the results are verified.  A pass\fail 
     test status is returned from main.     
     @endverbatim
 *
 *      
 *   <b> Procedure to run the example </b>
 *   @verbatim
     1. Configure the CCS setup to work with the emulator being used
     2. Please refer CCS manual for setup configuration and loading 
        proper GEL file
     3. Launch CCS window
     4. Open project Mcbsp_example.pjt
     5. Build the project and load the .out file of the project.
     @endverbatim
 *
 * =============================================================================
 **/

#include <csl_types.h>
#include <soc.h>
#include <c6x.h>
#include <cslr_sys.h>
#include <cslr_intc.h>
#include <cslr_mcbsp.h>
#include <stdio.h>
#include <cslr_psc.h>

#define NUM_WORDS   4
volatile int intFlag=1;
volatile int intFlag0=1;
Uint32 transBuff[4] = {0x5A5A5A5A,0x87654321,0x11223344,0x55667788};
Uint32 trans_val[NUM_WORDS] ;
Uint32 rec_val[NUM_WORDS] ;
Uint32 rec_val0[NUM_WORDS] ;


static void device_init(void); 
static void init_mcbsp(void);   
static int test_mcbsp(void);   
extern void intcVectorTable(void);

CSL_McbspRegsOvly mcbsp0Regs = (CSL_McbspRegsOvly)CSL_MCBSP_0_REGS;
CSL_McbspRegsOvly mcbsp1Regs = (CSL_McbspRegsOvly)CSL_MCBSP_1_REGS;
CSL_IntcRegsOvly intcRegs = (CSL_IntcRegsOvly)CSL_INTC_0_REGS;

int main (void) 
{
  //enable mcbsp0 in power and sleep controller
  device_init(); 
  
  //setup mcbsp registers and start mcbsp running 
  init_mcbsp();
  
  //test loopback, returns 0 for pass and 1 for fail 
  return(test_mcbsp());
}

void init_mcbsp(void)
{
	int i;
	//serial port control register SPCR
   CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_RRST,DISABLE);    		//receiver enable
   CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_XRST,DISABLE);    		//transmitter enable
   CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_GRST,RESET);      		//SRGR out of reset
   CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_FRST,RESET);       	//enable frame sync

   //mcbsp0Regs->SPCR = CSL_FMKT(MCBSP_SPCR_DLB,ENABLE);    	   //enable loopback mode
   mcbsp0Regs->SPCR = CSL_FMKT(MCBSP_SPCR_CLKSTP,DELAY);    	   //enable clk stop mode with NODELEY or DELAY
                 
  // receive control register                
  //mcbsp0Regs->RCR = CSL_FMKT(MCBSP_RCR_RWDLEN1,32BIT)   	//receive word 32bit
  //	  	  	  	  	| CSL_FMK(MCBSP_RCR_RFRLEN1,NUM_WORDS);   		//1st Phase frame length RFRLEN1
  //CSL_FINST(mcbsp0Regs->RCR, MCBSP_RCR_RDATDLY,1BIT);    	//receive data delay 1bit

  //transmit control register
  mcbsp0Regs->XCR = CSL_FMKT(MCBSP_XCR_XWDLEN1,32BIT)		//trans word 32bit
				    |CSL_FMK(MCBSP_XCR_XFRLEN1,0);   		//1st Phase frame length XFRLEN1
  CSL_FINST(mcbsp0Regs->XCR, MCBSP_XCR_XDATDLY,1BIT);    	//trans data delay 1bit

  
  //sample rate generator SRGR
  mcbsp0Regs->SRGR = CSL_FMKT(MCBSP_SRGR_CLKSM,INTERNAL) 	//internal clock, defualt CLKG
				  //| CSL_FMKT(MCBSP_SRGR_FSGM,DXR2XSR)     	//(FSGM  = DXR2XSR or FSG, FSX is generated only when DXR to XSR copy)
				  //| CSL_FMKT(MCBSP_SRGR_GSYNC,FREE)       	//(GSYNC  = FREE or SYNC, Sample rate generator is free running, defualt FREE)
				  //| CSL_FMKT(MCBSP_SRGR_CLKSP,RISING)     	//(CLKSP  = RISING or FALLING, CLKS polarity is used only when clks are external, defualt RISING )
                  //| CSL_FMK(MCBSP_SRGR_FPER,63)         	//frame period
                  //| CSL_FMK(MCBSP_SRGR_FWID,31)         	//frame width
                  | CSL_FMK(MCBSP_SRGR_CLKGDV,99);      		//clock divider value

  mcbsp0Regs->SRGR |= (0 << 31);    	// (GSYNC = 0, Sample rate generator is free running)
  mcbsp0Regs->SRGR |= (0 << 30);    	// (CLKSP = 0, CLKS polarity is used only when clks are external)
  mcbsp0Regs->SRGR |= (0 << 28);    	// (FSGM  = 0, FSX is generated only when DXR to XSR copy)

  //pin control register
  mcbsp0Regs->PCR = CSL_FMKT(MCBSP_PCR_FSXM,  INTERNAL)    		//internal frame sync defualt EXTERNAL
				 //| CSL_FMKT(MCBSP_PCR_FSRM,EXTERNAL)     		//internal fram sync defualt EXTERNAL
                 //| CSL_FMKT(MCBSP_PCR_CLKRM,INPUT)      		//internal fram sync defualt INPUT
                 | CSL_FMKT(MCBSP_PCR_CLKXM,  OUTPUT)     		//trans clock mode
                 | CSL_FMKT(MCBSP_PCR_FSXP,   ACTIVELOW)   		//ACTIVELOW or ACTIVEHIGH, FSX polarity is used only when clks are external, defualt RISING
                 | CSL_FMKT(MCBSP_PCR_CLKXP,  RISING)     		//RISING or FALLING, CLKS polarity is used only when clks are external, defualt RISING
  	  	  	  	 | CSL_FMKT(MCBSP_PCR_SCLKME, NO);       		//sample clock mode selection bit defualt NO, else BCLK to set 1

  // McBSP 1 config
#if 1
  	//serial port control register SPCR

    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_RRST,DISABLE);     	//receiver enable
    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_XRST,DISABLE);     	//transmitter enable
    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_GRST,RESET);       	//SRGR out of reset
    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_FRST,RESET);       	//enable frame sync

    //mcbsp1Regs->SPCR = CSL_FMKT(MCBSP_SPCR_DLB,ENABLE);    	//enable loopback mode
    mcbsp1Regs->SPCR = CSL_FMKT(MCBSP_SPCR_CLKSTP,DELAY);  	//enable clk stop mode with NODELEY or DELAY

    // receive control register
    mcbsp1Regs->RCR = CSL_FMKT(MCBSP_RCR_RWDLEN1,32BIT)   		//receive word 32bit
					  | CSL_FMK(MCBSP_RCR_RFRLEN1,0);   		//1st Phase frame length RFRLEN1
    CSL_FINST(mcbsp1Regs->RCR, MCBSP_RCR_RDATDLY,0BIT);    		//receive data delay 1bit

    //transmit control register
    //mcbsp1Regs->XCR = CSL_FMKT(MCBSP_XCR_XWDLEN1,32BIT)	    	//trans word 32bit
	//				  | CSL_FMK(MCBSP_XCR_XFRLEN1,NUM_WORDS);   		//1st Phase frame length XFRLEN1
    //CSL_FINST(mcbsp1Regs->XCR, MCBSP_XCR_XDATDLY, 0BIT);    	//trans data delay 1bit

    //sample rate generator SRGR
    mcbsp1Regs->SRGR = CSL_FMKT(MCBSP_SRGR_CLKSM,INTERNAL) 		//internal clock, defualt CLKG
    				  //| CSL_FMK(MCBSP_SRGR_FSGM,DXR2XSR)     	//(FSGM  = DXR2XSR or FSG, FSX is generated only when DXR to XSR copy)
    				  //| CSL_FMK(MCBSP_SRGR_GSYNC,FREE)       	//(GSYNC  = FREE or SYNC, Sample rate generator is free running, defualt FREE)
    				  //| CSL_FMK(MCBSP_SRGR_CLKSP,RISING)     	//(CLKSP  = RISING or FALLING, CLKS polarity is used only when clks are external, defualt RISING )
                      //| CSL_FMK(MCBSP_SRGR_FPER,63)         	//frame period
                      //| CSL_FMK(MCBSP_SRGR_FWID,31)         	//frame width
                      | CSL_FMK(MCBSP_SRGR_CLKGDV,12);      		//clock divider value


    //pin control register
    mcbsp1Regs->PCR = CSL_FMKT(MCBSP_PCR_FSXM,  EXTERNAL)    	//internal frame sync defualt EXTERNAL
    				 //| CSL_FMKT(MCBSP_PCR_FSRM,EXTERNAL)     	//internal fram sync defualt EXTERNAL
                     //| CSL_FMKT(MCBSP_PCR_CLKRM,INPUT)      	//internal fram sync defualt INPUT
                     | CSL_FMKT(MCBSP_PCR_CLKXM,  INPUT)     	//trans clock mode
                     | CSL_FMKT(MCBSP_PCR_FSXP,   ACTIVELOW)   	//ACTIVELOW or ACTIVEHIGH, FSX polarity is used only when clks are external, defualt RISING
                     | CSL_FMKT(MCBSP_PCR_CLKXP,  RISING)     	//RISING or FALLING, CLKS polarity is used only when clks are external, defualt RISING
      	  	  	  	 | CSL_FMKT(MCBSP_PCR_SCLKME, NO);       	//sample clock mode selection bit defualt NO, else BCLK to set 1


    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_GRST,CLKG);      //SRGR out of reset
    for ( i = 0; i < 200; i++ ) { i++; }
    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_RRST,ENABLE);    //receiver enable
    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_XRST,ENABLE);    //transmitter enable
    for ( i = 0; i < 200; i++ ) { i++; }
    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_FRST,FSG);       //enable frame sync
#endif
  //start the mcbsp running
  CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_GRST,CLKG);      //SRGR out of reset
  for ( i = 0; i < 200; i++ ) { i++; }
  CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_RRST,ENABLE);    //receiver enable
  CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_XRST,ENABLE);    //transmitter enable
  for ( i = 0; i < 200; i++ ) { i++; }
  CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_FRST,FSG);       //enable frame sync

#ifdef INTTERUPT
  // map TIMER0 event to cpu int4
  //CSL_FINS(intcRegs->INTMUX1, INTC_INTMUX1_INTSEL4, 51); // 51
  CSL_FINS(intcRegs->INTMUX1, INTC_INTMUX1_INTSEL4, 49);

  /*
  48 MBXINT0 McBSP0 Transmit 112 Reserved
  49 MBRINT0 McBSP0 Receive 113 PMC_ED C64x+ PMC
  50 MBXINT1 McBSP1 Transmit 114 Reserved
  51 MBRINT1 McBSP1 Receive
*/
  // set ISTP to point to the vector table address
  ISTP = (unsigned int)intcVectorTable;

  // clear all interrupts, bits 4 thru 15
  ICR = 0xFFF0;

  // enable the bits for non maskable interrupt and CPUINT4 */
  IER |= 0x12;
  //IER |= 0x22;

  // enable interrupts, set GIE bit
  _enable_interrupts();
#endif
}

int test_mcbsp(void)
{
    int i;

    printf("\nTesting mcbsp loopback SDK\n\n");

    // mcbsp 0 transmit and mcbsp 1 receive
    for(i=0;i<NUM_WORDS;i++)
    {
    	trans_val[i] = transBuff[i];
        //poll transmitter ready
        while(CSL_FEXT(mcbsp0Regs->SPCR,MCBSP_SPCR_XRDY)
             != CSL_MCBSP_SPCR_XRDY_YES);

        //write to transmit register
        mcbsp0Regs->DXR = trans_val[i];

        //poll receiver is ready
        while(CSL_FEXT(mcbsp1Regs->SPCR,MCBSP_SPCR_RRDY)  != CSL_MCBSP_SPCR_RRDY_YES);
        rec_val[i] = mcbsp1Regs->DRR;

       //while(intFlag != 0);
       //   	intFlag = 1;

    }

    //check results
    for(i=0;i<NUM_WORDS;i++)
    {
        if(trans_val[i]==rec_val[i])
            printf("transmit: 0x%x   receive: 0x%x\n",trans_val[i],rec_val[i]);
        else
           {
             printf(" error\n");
             printf("\nMCBSP Loopback Test:  FAILED\n");
             printf("transmit: 0x%x   receive: 0x%x\n",trans_val[i],rec_val[i]);
             return(1);
           }
    }

    // mcbsp 1 transmit and mcbsp 0 receive
    for(i=0;i<NUM_WORDS;i++)
    {
    	rec_val0[i] = 0;
    	trans_val[i] = transBuff[i];
        //poll transmitter ready
        while(CSL_FEXT(mcbsp1Regs->SPCR,MCBSP_SPCR_XRDY)   != CSL_MCBSP_SPCR_XRDY_YES);

        //write to transmit register
        mcbsp1Regs->DXR = trans_val[i];
        printf("transmit: 0x%x\n",trans_val[i]);
        //poll receiver is ready
        while(CSL_FEXT(mcbsp0Regs->SPCR,MCBSP_SPCR_RRDY)  != CSL_MCBSP_SPCR_RRDY_YES);
        rec_val0[i] = mcbsp0Regs->DRR;
        printf(" receive: 0x%x\n",rec_val0[i]);

       //while(intFlag0 != 0);
       // 	intFlag0 = 1;

    }

    //check results
    for(i=0;i<NUM_WORDS;i++)
    {
        if(trans_val[i]==rec_val0[i])
            printf("transmit: 0%x   receive: 0x%x\n",trans_val[i],rec_val0[i]);
        else
           {
             printf(" error\n");
             printf("\nMCBSP Loopback Test:  FAILED\n");
             printf("transmit: 0x%x   receive: 0x%x\n",trans_val[i],rec_val0[i]);
             return(1);
           }
    }

    printf("\nMCBSP Loopback Test:  PASSED\n");
    
    return(0);
}

#if 1
int j = 0;
interrupt void interrupt4(void)
{
  // disable TIMER0 1:2 side
  //CSL_FINST(tmr0Regs->TCR,TMR_TCR_ENAMODE12,DISABLE);

  //read receive register
   rec_val[j++] = mcbsp1Regs->DRR;
  // set the interrupt flag
  intFlag=0;
}

int k = 0;
interrupt void interrupt5(void)
{
  // disable TIMER0 1:2 side
  //CSL_FINST(tmr0Regs->TCR,TMR_TCR_ENAMODE12,DISABLE);

  //read receive register
   rec_val0[k++] = mcbsp0Regs->DRR;
  // set the interrupt flag
  intFlag0=0;
}
#endif
void device_init(void) 
{
  
  CSL_PscRegsOvly pscRegs = (CSL_PscRegsOvly)CSL_PSC_0_REGS;

  // deassert MCBSP0 local PSC reset and set NEXT state to ENABLE
  pscRegs->MDCTL[CSL_PSC_MCBSP0] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE )
                                 | CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );
 
  //move MCBSP0 PSC to Next state
  pscRegs->PTCMD = CSL_FMKT(  PSC_PTCMD_GO0, SET );
 
  //wait for transition
  while ( CSL_FEXT( pscRegs->MDSTAT[CSL_PSC_MCBSP0], PSC_MDSTAT_STATE )
          != CSL_PSC_MDSTAT_STATE_ENABLE );

	// deassert MCBSP1 local PSC reset and set NEXT state to ENABLE
	pscRegs->MDCTL[CSL_PSC_MCBSP1] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE )
								   | CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );

	//move MCBSP1 PSC to Next state
	pscRegs->PTCMD = CSL_FMKT(  PSC_PTCMD_GO0, SET );

	//wait for transition
	while ( CSL_FEXT( pscRegs->MDSTAT[CSL_PSC_MCBSP1], PSC_MDSTAT_STATE )
			!= CSL_PSC_MDSTAT_STATE_ENABLE );

}

0 Sivaraj Kuppuraj over 11 years ago in reply to Naresh Patel1

TI__Mastermind 35645 points

Hi Naresh,

As i already answered in my earlier post that, it would be possible to send data from SPI slave to SPI master in full duplex mode but you will have limitations in meeting the desired data throughput.

Actually to work in McBSP SPI slave mode which would require DM6437 McBSP CLKG and it is 8 times faster than the CLKX/CLKR (from the SPI master) the DM6437 McBSP which is capable enough to handle the data sent from the SPI master but we cannot guarantee the benchmarked data thrroughput in full duplex mode.

Thanks & regards,

Sivaraj K

0 Naresh Patel1 over 11 years ago in reply to Sivaraj Kuppuraj

Intellectual 330 points

Hi Shivraj,

Thank you very much for your response.

Still you haven't answer my Question.

If data transfer from Slave to Master is possible then how?????????????

I already set the SPI Slave (McBSP1) CLKG 8 times faster than SPI Master(McBSP1). Slave MCBSP1 CLKG is 8.25MHz and master McBSP0 CLKG is 1MHz.. In this case data transfer is possible from master to slave but whz master is not able to receive data from slave.

I don't need data throughput. I just need to send couple of bytes only from SPI Slave (McBSP1) to SPI Master (McBSP0). i.e Slave just need to send acknowledge of data received from master.

Please have look into the code for all the config. Can you please help to figure out if it is possible then why SPI master is not able to receive the data from spi slave????

Thank you and regards,

Naresh

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DM6437 EVM: full duplex communication between McBSPs as SPI Master and Slave