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How many MAC operations are possible in C67x+ processor.



Dear all,

      I need to optimize the floating point c code. I am able to implement using two macs per cycle. Is there any possibility to have more number of macs per cycle. what is the limit of number of floating point macs in c67x+?

Regards,

Nagarjuna

 

  • Nagarjuna,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages. Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.

    If you choose a specific device, then you can look at its datasheet to determine the maximum number of floating point operations that can be executed in time (MFLOPS), then divide that by the clock rate to determine the number of floating point operations per cycle. Please choose a specific device.

    Reading the C67x+ CPU & Instruction Set Reference Guide, you can find the instructions that can be executed on each of the 8 execution units. Some instructions are only executed on one type, such as MPYSP on  .M1 & .M2, which other instructions can be executed on more than one type, such as ADDSP on .L1 & .L2 & .S1 & .S2.

    The TI C Compiler is very good at spreading these out across the various execution units to achieve the best performance, if that is how you are optimizing your code.

    You can also look for other similar operations that can be executed on different execution units, such as the RSQRSP on .S1 & .S2. These can execute at the same time as the MPYSP instruction on .M1 & .M2 and the ADDSP on .L1 & .L2, for example.

    You have optimized your code quite well, so I question the motivation behind your statement that you "need to optimize the floating point C code". Realistic performance depends more on the application software's system architecture and on the hardware's system architecture, so a hard, finite number is not interesting to me.

    Regards,
    RandyP