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Hugepage and TLB Lock support for OMAP5?

HU Jianan
Prodigy 120 points

Hi,

Currently, I am doing research on memory management on OMAP5. I want to know whether OMAP5 supports the Hugepage or not? 

Another question is about the OMAP5 processor TLB lock mechanism. Based on official ARM Cortex-A15 Technical Reference Manual, it says "The Cortex-A15 MMU does not support the locking of TLB entries at either Level 1 or Level 2". However, on OMAP543x Technical Reference Manual, it lists the "TLB Entry Lock Mechanism" (Page 4478). Is it mean that I can lock TLB through MMU_LOCK, MMU_CAM and MMU_RAM?

Thanks!

Best Regards,

Jianan

  • 0
    TI__Mastermind 29520 points

    Hello Jianan,

    Yes, OMAP5 supports "Huge page". The MMU supports different page sizes: large, medium, and small.

    Define the page size by register MMU_CAM[1:0] PAGESIZE 1:0
    Page size
    0x0: Section (1 MiB)
    0x1: Large page (64 KiB)
    0x2: Small page (4 KiB)
    0x3: Supersection (16 MiB)

    MMU_LOCK register locks some of the TLB entries

    MMU_RAM register holds a RAM entry

    MMU_CAM register holds a CAM entry

    For example see the MMU for DSP subsystem (section 5.3.2.5 Attribute MMU Overview in OMAP5 TRM) - The attribute MMU for the shared cache - SCACHE_MMU_DSP, provides the multi-access cache with a region-based address translation, read/write control, access type control, endiannism, and multilevel cache maintenance.

    The page sizes for the 17 entries are:
    • Large pages (eight): The page size supported is 512 MiB.
    • Medium pages (seven): The page sizes supported are 128 KiB and 1 MiB.
    • Small pages (two): The page sizes supported are 4 KiB and 32 KiB.
    The size of the page is configured by setting:
    • SCACHE_MMU_LARGE_POLICY_i[1] SIZE
    • SCACHE_MMU_MED_POLICY_j[1] SIZE
    • SCACHE_MMU_SMALL_POLICY_k[1] SIZE

    Best regards,

    Yanko