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transfer SRIO data to FPGA

keshav vetapalem
Prodigy 40 points

Hi Sir,

I want to transfer SRIO data to FPGA. I want to transfer at a constant rate (something like 24 bytes/512ns) from DSP memory to FPGA. For this kind of transfer SWRITE would be more appropriate.

Please provide me example/demo project and appropriate driver files in such a way that:

1. DSP will configure the buffer start address, buffer depth

2. Will program the rate at which transfer should happen

3. Packet size for each transfer will be programmed

4. DSP will initiate the transfer at the beginning.

5. All other SWRITE transaction should happen automatically without DSP software intervention.

Regards,

Keshav

  • 0
    TI__Mastermind 28085 points

    Hi Keshav,

    TI provide example/demo projects for test the SRIO peripheral, but it should not properly matching on your requirement.

    Refer below MCSDK example/demo projects.

    1. \ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\SRIO_TputBenchmarkingTestProject

    (Refer \ti\pdk_C6678_1_1_2_6\packages\ti\drv\srio\test\tput_benchmarking\Readme.txt to porting the example project to your design)

    2. \ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\SRIO_LoopbackTestProject

    3. \ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\SRIO_LoopbackDioIsrexampleproject

    If you want to run device to device SRIO transfer uncommand the below code(device_srio_loopback.c file) on 2 and 3 example projects.

    /* Configure SRIO ports to operate in loopback mode. */

    CSL_SRIO_SetLoopbackMode(hSrio, 0);

    CSL_SRIO_SetLoopbackMode(hSrio, 1);

    CSL_SRIO_SetLoopbackMode(hSrio, 2);

    CSL_SRIO_SetLoopbackMode(hSrio, 3);

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 40 points
    Ganapathi,
    Thanks for your answer.
    We have tried this projects and we are able to send NWRITE packets. (Each packet is initiated by DSP SW)
    However we are looking for a solution by which data from DSP memory will be transmitted over SRIO at a constant rate, with specified packet size without SW intervention.
    There was some examples for C64xx processors. DIO_Lib:
    http://processors.wiki.ti.com/index.php/DIO_Library
    But we are working on C6657. Any help on this will be highly appreciated.
  • 0 in reply to keshav vetapalem
    TI__Mastermind 28085 points

    Hi Keshav,

    That type of examples are not available in TI MCSDK package. Please modified the existing MCSDK example project to your requirement.

    I am not sure the C64xx processor example project is directly working on C66xx processor. Both processors RapidIO Interconnect Specification are different C66xx REV2.1.1 compliant and C64xx REV1.2 compliant. Please take a look at C64xx example code and understand the flow. Port the example code to C66xx processor.

    Thanks,