DM6437 EVM Slave is not able to transfer data to master

Naresh Patel1

Hello,

I am using DM6437 EVM to test SPI communication. I am not using TI driver code but I have modified the McBSP CSL example code for SPI communication.

To test the SPI communication, I have configured McBSP0 as a SPI master and McBSP1 as a SPI Slave as per the MCBSP user guide SPRU943c. I have also externally connected pins (transmit and receives) between McBSP0 and McBSP1 as per SPRU943c. I have successfully data transfer from McBSP0 (as SPI Master) to McBSP1( as SPI Slave) i.e means data transfer from SPI master to SPI slave. However I could not able to do data transfer from McBSP1 (as a SPI slave) to McBSP0 (as a SPI master). (i.e. data transfer from Slave to master). I am not able to receive single word at SPI master transmitted from SPI Slave.

I am trying to send few bytes from SPI slave to SPI master. But SPI master is not able to receive single byte from slave.

Can anybody please review my code and let me know what should i have to do so Slave can able to tranfer few words to master.

Fullscreen 3122.Mcbsp_example.c Download

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006, 2007
 *
 *   Use of this software is controlled by the terms and conditions found
 *   in the license agreement under which this software has been supplied.
 *  ============================================================================
 */

/** ============================================================================
 *   @brief A simple example to demonstrate CSL 3.x MCBSP register layer usage.
 *
 *   @file  mcbsp_example.c
 *
 *   <b> Example Description </b>
 *   @verbatim
     This example configures MCBSP0 in 32 bit loopback mode and uses software 
     polling to transmit and receive 32bit words. Four 32 bit words are 
     transmitted and received and the results are verified.  A pass\fail 
     test status is returned from main.     
     @endverbatim
 *
 *      
 *   <b> Procedure to run the example </b>
 *   @verbatim
     1. Configure the CCS setup to work with the emulator being used
     2. Please refer CCS manual for setup configuration and loading 
        proper GEL file
     3. Launch CCS window
     4. Open project Mcbsp_example.pjt
     5. Build the project and load the .out file of the project.
     @endverbatim
 *
 * =============================================================================
 **/

#include <csl_types.h>
#include <soc.h>
#include <c6x.h>
#include <cslr_sys.h>
#include <cslr_intc.h>
#include <cslr_mcbsp.h>
#include <stdio.h>
#include <cslr_psc.h>

#define NUM_WORDS   4
volatile int intFlag=1;
volatile int intFlag0=1;
Uint32 transBuff[4] = {0x5A5A5A5A,0x87654321,0x11223344,0x55667788};
Uint32 trans_val[NUM_WORDS] ;
Uint32 rec_val[NUM_WORDS] ;
Uint32 rec_val0[NUM_WORDS] ;


static void device_init(void); 
static void init_mcbsp(void);   
static int test_mcbsp(void);   
extern void intcVectorTable(void);

CSL_McbspRegsOvly mcbsp0Regs = (CSL_McbspRegsOvly)CSL_MCBSP_0_REGS;
CSL_McbspRegsOvly mcbsp1Regs = (CSL_McbspRegsOvly)CSL_MCBSP_1_REGS;
CSL_IntcRegsOvly intcRegs = (CSL_IntcRegsOvly)CSL_INTC_0_REGS;

int main (void) 
{
  //enable mcbsp0 in power and sleep controller
  device_init(); 
  
  //setup mcbsp registers and start mcbsp running 
  init_mcbsp();
  
  //test loopback, returns 0 for pass and 1 for fail 
  return(test_mcbsp());
}

void init_mcbsp(void)
{
	int i;
	//serial port control register SPCR
   CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_RRST,DISABLE);    		//receiver enable
   CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_XRST,DISABLE);    		//transmitter enable
   CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_GRST,RESET);      		//SRGR out of reset
   CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_FRST,RESET);       	//enable frame sync

   //mcbsp0Regs->SPCR = CSL_FMKT(MCBSP_SPCR_DLB,ENABLE);    	   //enable loopback mode
   mcbsp0Regs->SPCR = CSL_FMKT(MCBSP_SPCR_CLKSTP,DELAY);    	   //enable clk stop mode with NODELEY or DELAY
                 
  // receive control register                
  //mcbsp0Regs->RCR = CSL_FMKT(MCBSP_RCR_RWDLEN1,32BIT)   	//receive word 32bit
  //	  	  	  	  	| CSL_FMK(MCBSP_RCR_RFRLEN1,NUM_WORDS);   		//1st Phase frame length RFRLEN1
  //CSL_FINST(mcbsp0Regs->RCR, MCBSP_RCR_RDATDLY,1BIT);    	//receive data delay 1bit

  //transmit control register
  mcbsp0Regs->XCR = CSL_FMKT(MCBSP_XCR_XWDLEN1,32BIT)		//trans word 32bit
				    |CSL_FMK(MCBSP_XCR_XFRLEN1,0);   		//1st Phase frame length XFRLEN1
  CSL_FINST(mcbsp0Regs->XCR, MCBSP_XCR_XDATDLY,1BIT);    	//trans data delay 1bit

  
  //sample rate generator SRGR
  mcbsp0Regs->SRGR = CSL_FMKT(MCBSP_SRGR_CLKSM,INTERNAL) 	//internal clock, defualt CLKG
				  //| CSL_FMKT(MCBSP_SRGR_FSGM,DXR2XSR)     	//(FSGM  = DXR2XSR or FSG, FSX is generated only when DXR to XSR copy)
				  //| CSL_FMKT(MCBSP_SRGR_GSYNC,FREE)       	//(GSYNC  = FREE or SYNC, Sample rate generator is free running, defualt FREE)
				  //| CSL_FMKT(MCBSP_SRGR_CLKSP,RISING)     	//(CLKSP  = RISING or FALLING, CLKS polarity is used only when clks are external, defualt RISING )
                  //| CSL_FMK(MCBSP_SRGR_FPER,63)         	//frame period
                  //| CSL_FMK(MCBSP_SRGR_FWID,31)         	//frame width
                  | CSL_FMK(MCBSP_SRGR_CLKGDV,99);      		//clock divider value

  mcbsp0Regs->SRGR |= (0 << 31);    	// (GSYNC = 0, Sample rate generator is free running)
  mcbsp0Regs->SRGR |= (0 << 30);    	// (CLKSP = 0, CLKS polarity is used only when clks are external)
  mcbsp0Regs->SRGR |= (0 << 28);    	// (FSGM  = 0, FSX is generated only when DXR to XSR copy)

  //pin control register
  mcbsp0Regs->PCR = CSL_FMKT(MCBSP_PCR_FSXM,  INTERNAL)    		//internal frame sync defualt EXTERNAL
				 //| CSL_FMKT(MCBSP_PCR_FSRM,EXTERNAL)     		//internal fram sync defualt EXTERNAL
                 //| CSL_FMKT(MCBSP_PCR_CLKRM,INPUT)      		//internal fram sync defualt INPUT
                 | CSL_FMKT(MCBSP_PCR_CLKXM,  OUTPUT)     		//trans clock mode
                 | CSL_FMKT(MCBSP_PCR_FSXP,   ACTIVELOW)   		//ACTIVELOW or ACTIVEHIGH, FSX polarity is used only when clks are external, defualt RISING
                 | CSL_FMKT(MCBSP_PCR_CLKXP,  RISING)     		//RISING or FALLING, CLKS polarity is used only when clks are external, defualt RISING
  	  	  	  	 | CSL_FMKT(MCBSP_PCR_SCLKME, NO);       		//sample clock mode selection bit defualt NO, else BCLK to set 1

  // McBSP 1 config
#if 1
  	//serial port control register SPCR

    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_RRST,DISABLE);     	//receiver enable
    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_XRST,DISABLE);     	//transmitter enable
    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_GRST,RESET);       	//SRGR out of reset
    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_FRST,RESET);       	//enable frame sync

    //mcbsp1Regs->SPCR = CSL_FMKT(MCBSP_SPCR_DLB,ENABLE);    	//enable loopback mode
    mcbsp1Regs->SPCR = CSL_FMKT(MCBSP_SPCR_CLKSTP,DELAY);  	//enable clk stop mode with NODELEY or DELAY

    // receive control register
    mcbsp1Regs->RCR = CSL_FMKT(MCBSP_RCR_RWDLEN1,32BIT)   		//receive word 32bit
					  | CSL_FMK(MCBSP_RCR_RFRLEN1,0);   		//1st Phase frame length RFRLEN1
    CSL_FINST(mcbsp1Regs->RCR, MCBSP_RCR_RDATDLY,0BIT);    		//receive data delay 1bit

    //transmit control register
    //mcbsp1Regs->XCR = CSL_FMKT(MCBSP_XCR_XWDLEN1,32BIT)	    	//trans word 32bit
	//				  | CSL_FMK(MCBSP_XCR_XFRLEN1,NUM_WORDS);   		//1st Phase frame length XFRLEN1
    //CSL_FINST(mcbsp1Regs->XCR, MCBSP_XCR_XDATDLY, 0BIT);    	//trans data delay 1bit

    //sample rate generator SRGR
    mcbsp1Regs->SRGR = CSL_FMKT(MCBSP_SRGR_CLKSM,INTERNAL) 		//internal clock, defualt CLKG
    				  //| CSL_FMK(MCBSP_SRGR_FSGM,DXR2XSR)     	//(FSGM  = DXR2XSR or FSG, FSX is generated only when DXR to XSR copy)
    				  //| CSL_FMK(MCBSP_SRGR_GSYNC,FREE)       	//(GSYNC  = FREE or SYNC, Sample rate generator is free running, defualt FREE)
    				  //| CSL_FMK(MCBSP_SRGR_CLKSP,RISING)     	//(CLKSP  = RISING or FALLING, CLKS polarity is used only when clks are external, defualt RISING )
                      //| CSL_FMK(MCBSP_SRGR_FPER,63)         	//frame period
                      //| CSL_FMK(MCBSP_SRGR_FWID,31)         	//frame width
                      | CSL_FMK(MCBSP_SRGR_CLKGDV,12);      		//clock divider value


    //pin control register
    mcbsp1Regs->PCR = CSL_FMKT(MCBSP_PCR_FSXM,  EXTERNAL)    	//internal frame sync defualt EXTERNAL
    				 //| CSL_FMKT(MCBSP_PCR_FSRM,EXTERNAL)     	//internal fram sync defualt EXTERNAL
                     //| CSL_FMKT(MCBSP_PCR_CLKRM,INPUT)      	//internal fram sync defualt INPUT
                     | CSL_FMKT(MCBSP_PCR_CLKXM,  INPUT)     	//trans clock mode
                     | CSL_FMKT(MCBSP_PCR_FSXP,   ACTIVELOW)   	//ACTIVELOW or ACTIVEHIGH, FSX polarity is used only when clks are external, defualt RISING
                     | CSL_FMKT(MCBSP_PCR_CLKXP,  RISING)     	//RISING or FALLING, CLKS polarity is used only when clks are external, defualt RISING
      	  	  	  	 | CSL_FMKT(MCBSP_PCR_SCLKME, NO);       	//sample clock mode selection bit defualt NO, else BCLK to set 1


    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_GRST,CLKG);      //SRGR out of reset
    for ( i = 0; i < 200; i++ ) { i++; }
    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_RRST,ENABLE);    //receiver enable
    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_XRST,ENABLE);    //transmitter enable
    for ( i = 0; i < 200; i++ ) { i++; }
    CSL_FINST(mcbsp1Regs->SPCR,MCBSP_SPCR_FRST,FSG);       //enable frame sync
#endif
  //start the mcbsp running
  CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_GRST,CLKG);      //SRGR out of reset
  for ( i = 0; i < 200; i++ ) { i++; }
  CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_RRST,ENABLE);    //receiver enable
  CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_XRST,ENABLE);    //transmitter enable
  for ( i = 0; i < 200; i++ ) { i++; }
  CSL_FINST(mcbsp0Regs->SPCR,MCBSP_SPCR_FRST,FSG);       //enable frame sync

}

int test_mcbsp(void)
{
    int i;

    printf("\nTesting mcbsp loopback SDK\n\n");

    // mcbsp 0 transmit and mcbsp 1 receive
    for(i=0;i<NUM_WORDS;i++)
    {
    	trans_val[i] = transBuff[i];
        //poll transmitter ready
        while(CSL_FEXT(mcbsp0Regs->SPCR,MCBSP_SPCR_XRDY)
             != CSL_MCBSP_SPCR_XRDY_YES);

        //write to transmit register
        mcbsp0Regs->DXR = trans_val[i];

        //poll receiver is ready
        while(CSL_FEXT(mcbsp1Regs->SPCR,MCBSP_SPCR_RRDY)  != CSL_MCBSP_SPCR_RRDY_YES);
        rec_val[i] = mcbsp1Regs->DRR;

    }

    //check results
    for(i=0;i<NUM_WORDS;i++)
    {
        if(trans_val[i]==rec_val[i])
            printf("transmit: 0x%x   receive: 0x%x\n",trans_val[i],rec_val[i]);
        else
           {
             printf(" error\n");
             printf("\nMCBSP Loopback Test:  FAILED\n");
             printf("transmit: 0x%x   receive: 0x%x\n",trans_val[i],rec_val[i]);
             return(1);
           }
    }

    // mcbsp 1 transmit and mcbsp 0 receive
    for(i=0;i<NUM_WORDS;i++)
    {
    	rec_val0[i] = 0;
    	trans_val[i] = transBuff[i];
        //poll transmitter ready
        while(CSL_FEXT(mcbsp1Regs->SPCR,MCBSP_SPCR_XRDY)   != CSL_MCBSP_SPCR_XRDY_YES);

        //write to transmit register
        mcbsp1Regs->DXR = trans_val[i];
        printf("transmit: 0x%x\n",trans_val[i]);
        //poll receiver is ready
        while(CSL_FEXT(mcbsp0Regs->SPCR,MCBSP_SPCR_RRDY)  != CSL_MCBSP_SPCR_RRDY_YES);
        rec_val0[i] = mcbsp0Regs->DRR;
        printf(" receive: 0x%x\n",rec_val0[i]);


    }

    //check results
    for(i=0;i<NUM_WORDS;i++)
    {
        if(trans_val[i]==rec_val0[i])
            printf("transmit: 0%x   receive: 0x%x\n",trans_val[i],rec_val0[i]);
        else
           {
             printf(" error\n");
             printf("\nMCBSP Loopback Test:  FAILED\n");
             printf("transmit: 0x%x   receive: 0x%x\n",trans_val[i],rec_val0[i]);
             return(1);
           }
    }

    printf("\nMCBSP Loopback Test:  PASSED\n");
    
    return(0);
}

void device_init(void) 
{
  
  CSL_PscRegsOvly pscRegs = (CSL_PscRegsOvly)CSL_PSC_0_REGS;

  // deassert MCBSP0 local PSC reset and set NEXT state to ENABLE
  pscRegs->MDCTL[CSL_PSC_MCBSP0] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE )
                                 | CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );
 
  //move MCBSP0 PSC to Next state
  pscRegs->PTCMD = CSL_FMKT(  PSC_PTCMD_GO0, SET );
 
  //wait for transition
  while ( CSL_FEXT( pscRegs->MDSTAT[CSL_PSC_MCBSP0], PSC_MDSTAT_STATE )
          != CSL_PSC_MDSTAT_STATE_ENABLE );

	// deassert MCBSP1 local PSC reset and set NEXT state to ENABLE
	pscRegs->MDCTL[CSL_PSC_MCBSP1] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE )
								   | CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );

	//move MCBSP1 PSC to Next state
	pscRegs->PTCMD = CSL_FMKT(  PSC_PTCMD_GO0, SET );

	//wait for transition
	while ( CSL_FEXT( pscRegs->MDSTAT[CSL_PSC_MCBSP1], PSC_MDSTAT_STATE )
			!= CSL_PSC_MDSTAT_STATE_ENABLE );

}

I have attached my test code here with. Please do the needful ASAP.

P.S.

EVM DM6437 clock freq 594Mhz,

MCBSP freq 99MHz,

SPI Master (Mcbsp0) clock freq 1 MHz, clock divider value 99.

SPI Slave (Mcbsp1) clock freq 8.25 MHz, clock divider value 12.

Regards,

Naresh

over 11 years ago

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DM6437 EVM Slave is not able to transfer data to master