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eMMC Data CRC and drive strength settings

Anuroop Jesu
Intellectual 415 points

Hi there,

We have custom board with omap4470 and Toshiba eMMC[JEDEC/MMCA Version 4.5] component which is connected to MMC2 I/F [same as blaze board]. 

We are using the TI 4AJ.2.5.SP2 JB release. 

On doing the adb push or emmc bulk data write

e.g. 

dd if=/dev/zero of=/data/test

or 

dd if=/dev/zero of=/dev/block/platform/omap/omap_hsmmc.1/by-name/userdata

or to any other partition we see a dataCRC error

[ 582.424011] hsmmc: data -EILSEQ
[ 582.427734] hsmmc: status 608002 Timeout: 0 CRC 200000
[ 582.433471] hsmmc: host->data -699597580 host->response_busy 0
[ 582.440032] hsmmc: omap_hsmmc_reset_controller_fsm
[ 582.448608] mmcblk0: error -84 transferring data, sector 13981728, nr 1024, cmd response 0x900, card status 0xc00
[ 582.468078] MMC_BLK_CMD_ERR
[ 582.471679] end_request: I/O error, dev mmcblk0, sector 13981728
[ 582.478332] quiet_error: 118 callbacks suppressed
[ 582.483489] Buffer I/O error on device mmcblk0p11, logical block 1542656
[ 582.490875] lost page write due to I/O error on mmcblk0p11
[ 582.496917] end_request: I/O error, dev mmcblk0, sector 13981736
[ 582.503570] Buffer I/O error on device mmcblk0p11, logical block 1542657
[ 582.510894] lost page write due to I/O error on mmcblk0p11
[ 582.516998] end_request: I/O error, dev mmcblk0, sector 13981744
[ 582.523590] Buffer I/O error on device mmcblk0p11, logical block 1542658
[ 582.530975] lost page write due to I/O error on mmcblk0p11
[ 582.537017] end_request: I/O error, dev mmcblk0, sector 13981752
[ 582.543640] Buffer I/O error on device mmcblk0p11, logical block 1542659
[ 582.550964] lost page write due to I/O error on mmcblk0p11
[ 582.557067] end_request: I/O error, dev mmcblk0, sector 13981760
[ 582.563659] Buffer I/O error on device mmcblk0p11, logical block 1542660
[ 582.571044] lost page write due to I/O error on mmcblk0p11
[ 582.577148] end_request: I/O error, dev mmcblk0, sector 13981768
[ 582.583709] Buffer I/O error on device mmcblk0p11, logical block 1542661
[ 582.591125] lost page write due to I/O error on mmcblk0p11
[ 582.597137] end_request: I/O error, dev mmcblk0, sector 13981776
[ 582.603790] Buffer I/O error on device mmcblk0p11, logical block 1542662
[ 582.611114] lost page write due to I/O error on mmcblk0p11
[ 582.617218] end_request: I/O error, dev mmcblk0, sector 13981784
[ 582.623779] Buffer I/O error on device mmcblk0p11, logical block 1542663
[ 582.631164] lost page write due to I/O error on mmcblk0p11
[ 582.637207] end_request: I/O error, dev mmcblk0, sector 13981792
[ 582.643859] Buffer I/O error on device mmcblk0p11, logical block 1542664
[ 582.651245] lost page write due to I/O error on mmcblk0p11
[ 582.657287] end_request: I/O error, dev mmcblk0, sector 13981800 
[ 582.663909] Buffer I/O error on device mmcblk0p11, logical block 1542665

When we checked with Toshiba they asked to change the drive strength of  MMC2 signals.

Can MMC2 drive strength be changed? as per TRM there are no registers settings for MMC2.

Toshiba also  wanted to know what is MMC I/F speed, as per TRM for MMC it is 48MHz but in current  release MMC2 clocked to 96MHz [since emmc can support HS200] probed clock signal and it is 96MHz.  Can the 96MHz cause Data CRC?

Any input or suggestions will be of great help.

Regards

Anuroop Jesu

  • 0
    TI__Mastermind 29520 points

    Hello Anuroop,

    I checked your questions, but there is no control for MMC2.

    There are some very tiny differences in the switching characteristics for MMC1 and 2. In summary MMC1 was designed for SD cards and MMC2 was defined for eMMC.

    The MMC/SD/SDIO2 controller allows connecting MMC/SD/SDIO cards (only 1.8V cards) or an external device that uses the MMC/SD/SDIO interface (JC64, for example). The module is connected to the L3 interconnect (internal DMA enabled) and supports 1-, 4-, and 8-bit data transfers. The second instance also supports an external transceiver and provides direction signals for data and command. Using an external transceiver device precludes 8-bit transfer mode.

    Q1: Can MMC2 drive strength be changed? -

    No, there is no an option to change drive strength for MMC2.

    The only options for control MMC2 are:

    Some of the peripheral I/Os have the option to be supplied with a 1.2-V or 1.8-V power supply (VDDS through device external pads). The power supply level to the dual-voltage I/Os of different peripherals is configurable through bit fields in the CONTROL_CORE_PADCONF_MODE register in the CORE domain (SDMMC2 I/Os)
    CONTROL_CORE_PADCONF_MODE[22]  VDDS_DV_SDMMC2

    MMC2 control:
    CONTROL_MMC2[31] MMC2_FEEDBACK_CLK_SEL Feed_back clock select



    Q2: Can the 96MHz cause Data CRC? -

    The MMC/SD/SDIO host controller deals with MMC/SD/SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit, and checking for syntactical correctness.

    Supported data rates:
    • In MMC mode:
    – Up to 768 Mbps (96 MB/s), 8-bit DDR data transfer, with a clock running at 48 MHz
    – Up to 384 Mbps (48 MB/s), 8-bit SDR data transfer, with a clock running at 48 MHz
    • In SD mode:
    – Up to 384 Mbps (48 MB/s), 4-bit DDR data transfer with a clock running at 48 MHz
    – Up to 256 Mbps (32 MB/s), 4-bit SDR data transfer with a clock running at 64 MHz
    • In SDIO mode:
    – Up to 192 Mbps (24 MB/s) in high-speed mode, 4-bit data transfer with a clock running at 48 MHz
    – Up to 24 Mbps (3 MB/s) in default speed mode, 1-bit data transfer with a clock running at 24 MHz

    CRC status: The CRC result is sent by the card through the sdmmci_dat0 line when executing a write transfer. In the case of transmission error, occurring on any of the active data lines, the card sends a negative CRC status on sdmmci_dat0. In the case of successful transmission, over all active data lines, the card sends a positive CRC status on sdmmci_dat0 and starts the data programming procedure.
    Supported clock frequencies:
    • MMC mode:
    – Up to 48 MHz in DDR and SDR modes

    Could you check if MMCHS interface clock is enabled?

    Software must read capabilities (in boot ROM, for example) and is allowed to set (write) the MMCi.MMCHS_CAPA[26:24] and MMCi.MMCHS_CUR_CAPA[23:0] bit fields before the MMC/SD/SDIO host driver is started.

    Set the MMCHS default capabilities - Software must read capabilities (in boot ROM, for example) and is allowed to set (write) the MMCi.MMCHS_CAPA[26:24] and MMCi.MMCHS_CUR_CAPA[23:0] bit fields before the MMC/SD/SDIO host driver is started.


    Best regards,

    Yanko