I am a newer about AM335x gpmc driver.
Recently, I am going to realize the data transfer between AM335x and FPGA via gpmc. And got some trouble of the burst writing mode. I want to use burst writing mode. When I finish configing the GPMC registers Config1~Config7, the result got by FPGA shows that it is still in single writing mode. Can any one help me?
This is my config code:
static struct gpmc_timings fpga_timings = {/*GPMC timing configurations*/
.sync_clk = 10000,
.cs_on = 0,
.cs_rd_off = 23 * 10, /* Read deassertion time */
.cs_wr_off = 23 * 10, /* Write deassertion time */
/* ADV signal timings corresponding to GPMC_CONFIG3 */
.adv_on = 0, /* Assertion time */
.adv_rd_off = 2 * 10, /* Read deassertion time */
.adv_wr_off = 2 * 10, /* Write deassertion time */
/* WE signals timings corresponding to GPMC_CONFIG4 */
.we_on = 3 * 10, /* WE assertion time */
.we_off = 23 * 10, /* WE deassertion time */
/* OE signals timings corresponding to GPMC_CONFIG4 */
.oe_on = 3 * 10, /* OE assertion time */
.oe_off = 23 * 10, /* OE deassertion time */
/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
.page_burst_access = 1 * 10, /* Multiple access word delay */
.access = 7 * 10, /* Start-cycle to first data valid delay */
.rd_cycle = 23 * 10, /* Total read cycle time */
.wr_cycle = 23 * 10, /* Total write cycle time */
/* The following are only on OMAP3430 */
.wr_access = 7 * 10, /* WRACCESSTIME */
.wr_data_mux_bus = 3 * 10, /* WRDATAONADMUXBUS */
};
val = GPMC_CONFIG1_READMULTIPLE_SUPP;
val |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
val |= GPMC_CONFIG1_READTYPE_SYNC;
val |= GPMC_CONFIG1_WRITETYPE_SYNC;
val |= GPMC_CONFIG1_CLKACTIVATIONTIME(1);
val |= GPMC_CONFIG1_PAGE_LEN(2);
val |= GPMC_CONFIG1_DEVICESIZE_16;
val |= GPMC_CONFIG1_DEVICETYPE_NOR;
val |= GPMC_CONFIG1_MUXADDDATA;
gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG1, val);
if (gpmc_cs_set_timings(GPMC_CS, &fpga_timings) < 0)
{
printk(KERN_ERR "Failed gpmc_cs_set_timings for QuickLogic CAMIF device\n");
goto free;
}
val = gpmc_cs_read_reg(GPMC_CS, GPMC_CS_CONFIG6);
val &= 0xe0f0f030;
val |= 0x07030481;
gpmc_cs_write_reg(GPMC_CS, GPMC_CS_CONFIG6, val);
//The writing code is as follows:
memset(fpga_dev.user_buff, 0, USER_BUFF_SIZE);
if (copy_from_user(fpga_dev.user_buff, buff, len))
{
status = -EFAULT;
goto fpga_write_done;
}
/* do something with the user data */
printk("fpga_write \n");
for (i = 0; i < 2; i=i+1)
{
ptr=fpga_dev.user_buff;
writesw(fpga_base+i*4,ptr,4);
}
The result got by FPGA is as follows:
the picture shows that the gpmc_clk is 100MHz, it is in single mode ,why ,can anyone help me ?
