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vrajesh parikh said:I am using the DSP TMS320C6455 - 1GHz. DSK board.In my software, I try to measure the time taken by the one "_nop(); " instruction. then I found that one "_nop()" instruction takes 10 nsec time. As my DSP is at 1GHz, one "_nop()" should take 1 nsec only. What could be the problem ?
A couple of consideration:
- It is not easy to benchmarks the execution time of 1 single instruction as the CPU as a pipeline. The instruction need to be fetched, decoded and executed by the CPU..
You should benchmark a longer code so that you are sure that at every CLK cycle at least an instruction (or more if executed in //) is executed.
- if the application is located in external memory then it takes much longer to fetch the code compared to when it is in internal memory.
As a test use the linker to place the code/data in internal memory (L1D/L1P).
Usually the final application resides in external memory but you either:
- Locate critical code/data in part of the internal memory
- Set external memory as cacheable and set part of the internal memory as cache
for more information see:
C64x/C64x+ DSP CPU and Instruction Set Reference Guide - SPRU732H
vrajesh parikh said:I also try to measure the EMIFA interface timing. I have connected the CE5 of the EMIFA with the CS of one buffer IC (74LVTH16245). and read the data of 74LVTH16245 IC. Also see the waveforms of the CE5 signal.I found the one IMIFA read cycle takes 130 nsec. Why this much time ? for verification I have measure the EMIFA clock source and found that it is at 100 MHz.(it is ok).
The read cycles is divided in 3 steps (setup, strobe, hold). Each of this steps can be programmable (in number of cycles) via some EMIF registers.
Please double check the EMIF register configuration to see if it matches with was you see on the timings. As far as I remember the minimum register value (ie fastest timing) is given in the EMIF user's guide - SPRU971C.
If you use a GEL file check the EMIF config used in the GEL file.