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I2S timing requirements and CLKPOL indication when in DSP format mode

AndMan
Intellectual 335 points


Hello, the C5505 I2S user guide indicates that the sampling / clocking edges of the I2S data is a function of both the CLKPOL and FRMT bits in the I2SSCTRL register. It appears that the timing requirement descriptions indicated in the C5505 datasheet which reference a given CLKPOL value may only be correct when FRMT=0 (I2S mode). When FRMT = 1 (DSP mode), the descriptions appear to be inverted.

If this is the case, which are the correct parameters to use for the frame sync signal timing requirements 9 and 10 when CLKPOL = 0 and FRMT = 1? My implementation matches that described on the following E2E post, and I want to make sure I am using the correct version of parameters 9 and 10: http://e2e.ti.com/support/dsp/c5000/f/109/p/119626/427368.aspx#427368


Thanks - AM

  • 0
    TI__Genius 12575 points

    Hi AndMan,

     For the configuration you have mentioned: Clock Pol = 0  & FRMT = DSP format :  

     Receive data will be sampled on the falling edge and transmit data shifted on the rising edge of the bit clock.

     And according to data sheet ( parameters 9 and 10) :

      tsu(FSV-CLKH)  = Setup time, I2S_FS valid before I2S_CLK high (CLKPOL = 0) ,

      th(CLKH-FSV) =  Hold time, I2S_FS valid after I2S_CLK high (CLKPOL = 0) -  which looks correct.

     Below is the snapshot for the above mentioned timing details from datasheet:

    Hope the information helps.

    Regards

     Vasanth