How to configure DM8148 to use discrete sync to capture video?

Hello,

You could check this e2e forum thread:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/163341.aspx

Best Regards,

Margarita

Hi Jemish,

You need to do following settings

sHwPortParam.eCaptMode          =  OMX_VIDEO_CaptureModeSC_DISCRETESYNC;
sHwPortParam.eVifMode              =  OMX_VIDEO_CaptureVifMode_24BIT;
sHwPortParam.eInColorFormat  =  OMX_COLOR_Format24bitRGB888;

sHwPortParam.eScanType           =  OMX_VIDEO_CaptureScanTypeProgressive;

and set remaining variables of this structure accordingly.

Thanks

Ram

Hi Ram,

I did same setting " OMX_VIDEO_CaptureModeSC_DISCRETESYNC"suggested by you for capture mode. I also probe hsync, vsysc, signal coming out of decoder (GS2971A) chip. But still I am unable to capture data. 

Am I missing anything? 

Regards,

Jemish

Hi Jemish,

Can you check with decoder tvp7002 in discrete sync mode? This has already been tested.

Not sure of your decoder GS2971A. How is this decoder integrated to VPSS?

Thanks

Ram

Hi Ram,

No, we have not checked wit TVP7002. We are very close to the solution so if we won't be able to succeed we will start exploring DM8148 EVM as well.

Decoder chip (GS2971A) is connected with DM VIN[1]A with HSync, VSync, Field, Clock, Data (D2-9 of GS to D0-D7 of DM & D12-19 of GS to D8-15 of DM). We have configured GS2971A in H:V:F Discrete Sync Mode and we verify (using Logic Analyzer) that all signals are generated properly.

DM8148 changes & Observation:

1. To configure DM to operate in Discrete Sync mode, we modify VIP_PARSER_PORT_A (Reg. Addr. : 0x48105a04) from 0xa114 to 0x1114.
2. This means, We modify the VSync polarity from LOW to HIGH, ACTVID polarity from HIGH to LOW and capture style from “ACTVID style line capture” to “HSYNC style line capture”.
3. With this changes, All progressive resolutions are working fine but we are facing issue in Interlaced resolution. We are getting video artifacts in left side of video if we want to do interlaced encoding with “bFieldMerged   = OMX_TRUE” and if I do progressive encoding with “bFieldMerged   = OMX_FALSE” I am not getting any artifacts.
4. We verify this with our YUV Capture Only demo as well.

Is there any more configurations in DM side which we are missing? We stuck with the bring-up of our board with this issue, please connect someone who worked on HDVPSS driver.

Thanks,

Hitesh

Hi Ram,

Any update regarding issue posted by Hitesh? We are not able to understand why same data (interlaced) captured differently (bFieldMerged= OMX_TRUE & bFieldMerged= OMX_FALSE ) create different behavior?

Regards,

Jemish

Hi,

     Have you tried capturing using V4L2 and then passing the video to OMX? I think that configuring the V4L2 capture driver is easier.

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/326172/1170437.aspx#1170437

-David