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Watchdog reseting earlier in SPL & u-boot in AM335x

We have a custom board based on beaglebone black,
We have watchdog issue in SPL & u-boot.

Watchdog in SPL and u-boot is set to expire after 60 secs,
but when we test we find that watchdog actually resets at 51 secs instead of 60 secs.

We doubt following, PLL configuration in the SPL.
Any suggestion/pointers would help us moving forward faster.

Thank you in advance!

Regards,
Ankur

  • Hi Ankur,

    You are right.

    1. Ensure to have correct clock settings in both SPL and u-boot for Watchdog.

    2. Ensure the programmed watchdog counter is value is right.

    Thanks.

  • Hi Rajasekaran,

    Thank you reply,

    We checked another thing in u-boot.
    I checked the msdelay function, i had given delay of 30 secs,
    but in this case actual delay is 34 seconds. Instead of 30 seconds.

    I started refering AM335x_TechnicalReferanceManual.pdf document for PLL settings, do i need to refer any other document for the same ?

    Thank you,

    Regards,
    Ankur

  • Hi Ankur,

    Do you have a AM335x EVM board?

    How did you measure the timing in u-boot as well watchdog timing ( how you are firing WDT) ? 

    How about your ARM clock speed than EVM ?

    Also, Try to cross check the timings from linux side through HR timers & normal timers drivers concept.

    Please cross check the timings with your EVM as well custom board by using WDT, delay fns (thr C code), sleep fns, etc.,

  • Hi Ankur,

    Check if the WD timer isn't clocked from the AM335X internal 32k oscillator. This can be very inaccurate.

  • Hi Titus,

    Sorry for late reply,
    No we dont have AM335X EVM board. :(
    Difference of timing was very huge(10 secs) so i was putting while(1) in the SPL/uboot and starting timer on my mobile.

    I am yet to check timer delay and correct the same.

    I will update the status here.

    Thank you,

    Regards,
    Ankur

  • Hi Biser,

    You are 100% right, watchdog timer was clocked from internal clock.
    When i changed the clock selection from regiter CLKSEL_WDT1_CLK, and tested it started working.

    I am yet to check why delay function is not accurate.
    I will udpate status here.

    Thank you very much.

    Regards,
    Ankur