TMDSEVM6657LS

We have created a daughter card to connect PCIe between TI 6657 Eval Brd and Xilinx FPGA Eval Brd.  We have been successful in getting link up without errors on both ends of link and are able to read and modify  configuration registers at endpoint (FPGA) and at Root Complex (DSP) but we have not been successful in writing small block of data to PCIe endpoint BRAM and confirming inbound data read back at Root Complex is good.  Basically memory readback is all 0s currently.  We are suspecting that hardware setup is good and that we are still missing some memory configuration register setup either on inbound/outbound side of link.  We were hoping someone could provide the critical configuration registers we need to be concerned with for this setup.  It appears that we also need to be using address space 1 on RC side for data transfer and we could not find a memory map for this address space.