McBSP1 Slave Mode Configuration

Hello Shajin,

If H_MCBSP1_CLK and H_MCBSP1_FSX lines are not active, therefore your MCBSP1 module is not initialized.

I suggest checking, the McBSP1 clock configuration by the registers in PRCM.

McBSP1 modules that are gated in the AUDIO power domain. McBSP1 belongs to Power Domain ABE - PD_ABE

To enable this power domain, set the register PM_ABE_PWRSTCTRL[1:0] POWERSTATE - 0x3 - ON State

Clock Domain State Transition Control  - CM1_ABE_CLKSTCTRL[1:0] CLKTRCTRL - 0x3 HW_AUTO: Automatic transition is enabled.

For McBSP1, the functional clock comes from the CLKS and CLKX signals. The choice between these two clocks is defined by the MCBSP1.MCBSPLP_PCR_REG[7] SCLKME bit and the MCBSP1.MCBSPLP_SRGR2_REG[13]
CLKSM bit.
The CLKS signal of McBSP1 is linked to an internal clock (MCBSP1_FCLK) provided by the PRCM module. The CLKS signal can also be linked to an external signal through the abe_clks pin of the device boundary.

PRCM.CM1_ABE_MCBSP1_CLKCTRL[1:0] in the PRCM registers. The clock is effectively cut, provided the other modules that receive it do not require it.

Software must ensure a consistent programming between the McBSPi.MCBSPLP_SYSCONFIG_REG[9:8] CLOCKACTIVITY bit field and the PRCM MCBSPi_FCLK and L4_ICLK control bits.

Mux MCBSP1_FCLK            - CM1_ABE_MCBSP1_CLKCTRL[25:24] CLKSEL_SOURCE
Mux MCBSP1_INT_FCLK   - CM1_ABE_MCBSP1_CLKCTRL[27:26] CLKSEL_INTERNAL_SOURCE

Check the McBSP1 pad multiplexing options by control module's registers:

CONTROL_CORE_PAD0_ABE_MCBSP2_FSX_PAD1_ABE_MCBSP1_CLKX[15:0]

CONTROL_CORE_PAD0_ABE_MCBSP2_FSX_PAD1_ABE_MCBSP1_CLKX[31:16]

CONTROL_CORE_PAD0_ABE_MCBSP1_DR_PAD1_ABE_MCBSP1_DX[15:0]

CONTROL_CORE_PAD0_ABE_MCBSP1_DR_PAD1_ABE_MCBSP1_DX[31:16]

CONTROL_CORE_PAD0_ABE_MCBSP1_FSX_PAD1_ABE_PDM_UL_DATA[15:0]

ABE McBSP1 Signal Group Parameter Controls to Different Interface I/O Pads Mapping

CONTROL_SMART3IO_PADCONF_3[31:30] SLIMBUS1_DR0_MB
                                                                                                                             ==>         abe_mcbsp1_clkx
CONTROL_SMART3IO_PADCONF_3[19] SLIMBUS1_DR0_LB

CONTROL_SMART3IO_PADCONF_3[29:28] SLIMBUS1_DR1_MB
                                                                                                                              ==>         abe_mcbsp1_dr
CONTROL_SMART3IO_PADCONF_3[15] SLIMBUS1_DR1_LB

CONTROL_SMART3IO_PADCONF_0[9:8] SDMMC3_DR0_MB                             abe_mcbsp1_dx;
CONTROL_SMART3IO_PADCONF_2[5] SDMMC3_DR0_LB                 ==>         abe_mcbsp1_fsx

See McBSP functions in following files:

/arch/arm/mach-omap2/ mcbsp.c

/sound/soc/omap/ omap-mcbsp.c

/sound/soc/omap/ mcbsp.c

static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
                   const char *src)
{
    u32 v;

    /*
     * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
     * mux) is used */
    v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);

    if (!strcmp(signal, "clkr")) {
        if (!strcmp(src, "clkr"))
            v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
        else if (!strcmp(src, "clkx"))
            v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
        else
            return -EINVAL;
    } else if (!strcmp(signal, "fsr")) {
        if (!strcmp(src, "fsr"))
            v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
        else if (!strcmp(src, "fsx"))
            v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
        else
            return -EINVAL;
    } else {
        return -EINVAL;
    }

    omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);

    return 0;
}

Apply the suggested settings in the listed registers above.

Best regards,

Yanko