How to configure Bus priority in C6670?

Hi,

The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable priority registers allow software configuration of the data traffic through the TeraNet. Note: Lower number means higher priority - PRI = 000b = urgent, Higher number means lower priority PRI = 111b = low.

Some masters do not have a priority allocation register of their own. For these masters, a priority allocation register is provided for them and described in the sections "4.4.1 Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register" on data manual.

In PCIe your understanding is correct, use MST_PRIORITY bits to set priority level. For other modules (CorePac and SRIO), see the respective User Guides. 

Thanks,

Hi Ganapathi,

Thank you for the reply and sorry for the delay.

May I ask again to make me sure?

I checked the CorePac User Guide and found the "MDMAARBU" register.
So, this is the register to configure the bus priority of CorePac against DDR3 and MSMC SRAM,
is it correct?

I have a question about the "PKTDMA_PRI_ALLOC" register.
SRIO doesn't have a priority allocation register,
so that I understood the PKTDMA_PRI_ALLOC is the right register to configure priority for SRIO.
My question is, will this priority be common to other master peripherals using PKTDMA
which doesn't have priority allocation register?
Because it seem there are no PKTDMA_PRI_ALLOC for each master peripheral.

best regards,
g.f.

Hi,

Ans1: Yes your understanding is correct. 

Note: It is a requirement to have urgent-priority (UPRI) field less than or equal to normal-priority (PRI) field. To ensure that, incorrect writes to MDMAARBU register where the numerical value of MDMAARBU.PRI is greater than MDMAARBU.UPRI will be dropped and will trigger a DSP memory protection fault from L2 memory controller. The values of priority fields will not be auto-corrected by L2 memory controller. The old value of MDMAARBU register will be retained.

Ans2: SRIO doesn't have a priority allocation register inside the IP. The priority level for transaction from this master port is described by PKTDMA_PRI_ALLOC register.

Thanks,

Hi Ganapathi,

Thank you for the reply.

I'm clear with bus priority for CorePac.
But while serching for SRIO, I found register which is for configuring VBUS priority.

I'm sorry for asking again.
In SRIO User Guide(sprugw1b) page.161 "3.4.1 Peripheral Setting Control Register",
there is "CBA_TRAN_PRI" bit field.
Isn't this the bit field for configuring bus priority for SRIO?

best regards,
g.f.

Hi,

This CBA_TRAN_PRI Bit field is used to set the DSP System transaction priority. 0 implies Highest Priority while 7 implies lowest. This Bit field also one of the parameter for bus priority of SRIO Peripheral.

Use the following SRIO LLD function to set VBUS priority.

// Set the transaction priority to be HIGHEST
    CSL_SRIO_SetTransactionPriority (hSrio, 0);

// Set the transaction priority to be LOWEST
    CSL_SRIO_SetTransactionPriority (hSrio, 7);

Thanks,

Hi Ganapathi,

Sorry I'm little confused.

Is my understanding correct?
1.If using peripheral EDMA or CPU to transfer data from SRIO, the CBA_TRAN_PRI will affect to the bus priority?

2.PKTDMA_PRI_ALLOC will affect when PKTDMA are accessing to linking RAM(DDR3 or L2), is it correct?

3.I found "Priority Control Register" in Multicore Navigator.
Is this register also bus priority parameter for SRIO and other Packet DMA based peripheral?
If yes, is this priority level common to all peripheral?

I'm very sorry for asking many time.

best regards,
g.f.