query on memory related issue

Hi,

Could you please tell me that what problem are you facing ?

So that, It is easy to us to clarify better way.

Hi,

Thanks for your post.

Please refer the DSP cache user guide in which you can find a way to determine Read/Write misses and hits on both L1D cache & L2 cache memory. Kindly refer sections 1.7.3.1, 1.7.3.2, 1.7.3.3, 1.7.3.4 for L1 D cahce and refer sections 1.7.4.1, 1.7.4.2 for L2 cache in the cache user guide as below:

http://www.ti.com/lit/ug/sprug82a/sprug82a.pdf

I hope, you will get all details in determining cache misses/hits on L1D/L2 cache memory.

Also, you could use profile count feature in CCS to determine the cycle hits of one cache misses.

Thanks & regards,

Sivaraj K

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Thanks for the info, 

I read through the DSP cache user guide sprug82a.pdf , but couldn't find any info on how to profile the cache hits/misses programmatically.

Is there a way to read the TAG register field , is it memory mapped?

Moreover i am working on ARM side and i presume this document applies for arm aswell.