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XIP Boot: High-Order Address Handling (GPMC_A[27:13] Pins)

Milan Bajza
Expert 1396 points


Hello,

I am working on customer hardware with DM8148 Rev. 3.0 and I want use a 64MByte NOR memory for booting a second level bootloader. It has a 16bit data bus and a non-muxed address bus.

For using the high order address lines TI has recomanded in past to use external 1kOhm pull downs for GPMC_A13 to GPMC_A25. I think that it is not necessary, with BTMODE[10]=1 (Option B). In this mode the internal pull down resistors are active during and after RBL booting.

In the errata sheet Advisory 3.0.33 there is no information about the configuration of the BTMODE[10]. Is it possible that the workaround is important only for the "Option A"? Or is the error independent of this mode?

Thanks,

Milan

  • 0
    TI__Guru**** 170625 points

    Hi Milan,

    Milan said:
    Is it possible that the workaround is important only for the "Option A"?

    I think the workaround is important also for "Option B", but under some additional conditions:

    GPMC_A13 (M1) (pin AF27) can be IPU in "Option B" when BTMODE[14:13] = 01b or 10b (Mux)

    GPMC_A14 M1 (pin AG28) can be IPU in "Option B" when BTMODE[14:13] = 01b or 10b (Mux)

    GPMC_A[27]/GPMC_A[23]  (pin R24) is IPU, thus external PD is needed in case this pin will be used

    GPMC_A[24] (M1) (pin M25) is IPU, thus external PD is needed in case this pin will be used

    GPMC_A[25] (M1) (pin K28) is IPU, thus external PD is needed in case this pin will be used

    As a general rule we have:

    XIP boot GPMC High order address bit handling –

    As described in section 4.7.2.2 of the DM814x TRM, the ROM code does not multiplex high order address lines gpmc_a[27:13] to their address functions, although the external memory device generally needs to see logic "0" on its higher order address bits to correctly address memory. Many of the high order address pads default to internal pull-down active; however, some pins will default to internal pull-up active and therefore will need to be driven or pulled low by external hardware for the duration of XIP boot operation. See the device data manual for specific details.

    Then are two approaches to successfully perform XIP boot

    a. Add external pull down resistors on GPMC lines which default to pullup so that the high order address lines will be logical 0 during ROM execution

    b. Add an external mux on XIP memory address lines to force 0 state on high order address lines during ROM execution. Note that user code would need to control this mux in user code (via gpio control) before accessing GPMC address above 4KB. In both cases above the user code needs to re-mux the high order address lines appropriately within the first 4KB of execution (in code space where high order bits are supposed to be zero)

    If in your case all GPMC_A high address pins (that you will use) default to IPD, no external PD is needed.

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Expert 1396 points

    Thank you Pavel, for your fast answer.

    "If in your case all GPMC_A high address pins (that you will use) default to IPD, no external PD is needed."

    Yes, I use the (M0) address lines with documented IPD as default. BTMODE[4:0] = 11011 XIP w/WAIT (MUX0). 

    So it means, that the documentation in the Table 4-2 " XIP (on GPMC) Boot Options" is correct. So far I was not sure.

    Regards,

    Milan